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Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.

The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (ΔVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (ΔNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower ΔNit than HfO2 device. However, the ΔNit contribution to the total ΔVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric.

We propose the bipolar-mode operation of resistive random access memory devices in a purely oxygen-vacancy (V0)-controlled regime, which is achieved by very low compliance capping for forming/set transitions. This regime enables us to achieve a very low reset current of 10-100 nA, in which the governing mechanism for switching only involves the reversible drift of oxygen ions to and from oxygen soluble gate electrodes. The physical analysis of a gate stack in this V0 regime confirms the absence of metallic nanofilaments. These findings pave the way for the realization of ultralow switching power RRAM devices.

We propose the use of high-oxygen-solubility metalgate electrodes as a material of choice for high- gate stacks in order to prolong the time-dependent-dielectric-breakdown (BD) reliability. Our findings on n-channel metal-oxide-semiconductor devices with these gate electrodes reveal that the application of low negative bias stress after a soft-BD (SBD) event helps to restore the oxygen ions and passivate the oxygen vacancy traps that comprise the percolation path. This can be a simple yet effective designfor-reliability tool to initiate the self-repair of the percolation path and operate the circuit for a prolonged period after repair. The only requirement for achieving this SBD reversibility is to choose gate electrodes that can serve as good oxygen reservoirs.

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high- devices with TaN/TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness.

This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide (Dy2O3) cap layer with a thickness of 5 Aring on top of the SiON host dielectrics, Vt,lin of 0.18 V for long-channel devices (Lg = 1 mum) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The Vt modulation due to the Dy2O3 cap layer is also maintained in the short-channel devices (with an Lg,min of 90 nm as demonstrated in this letter). In particular, approximately 150times reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy2O3 cap layer on SiON dielectrics, likely due to a high-k layer (DySiON) formation during device source/drain activation process. We also report that the Dy2O3 layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.

The reliability of various Al/sub 2/O/sub 3/, ZrO/sub 2/ and Al/sub 2/O/sub 3//ZrO/sub 2/ double layers with a physical oxide thickness from 3 nm to 15 nm and TiN gate electrodes was studied by measuring time-to-breakdown using gate injection and constant voltage stress. The extracted Weibull slope /spl beta/ of the breakdown distribution is found to be below 2 and shows no obvious thickness dependence. These findings deviate from previous results on intrinsic breakdown in SiO/sub 2/, where a strong thickness dependence was explained by the percolation model. Although promising performance on devices with high-k layers as dielectric can be obtained, it is argued that gate oxide reliability is likely limited by extrinsic factors.