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We investigated the device performance of the optimized 3-nm gate length ( $L_{G})$ bulk silicon FinFET device using 3-D quantum transport device simulation. By keeping source and drain doping constant and by varying only the channel doping, the simulated device is made to operate in three different modes such as inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode. The excellent electrical characteristics of the 3-nm gate length Si-based bulk FinFET device were investigated. The subthreshold slope values (SS $\sim $ 65 mV/decade) and drain-induced barrier lowering (DIBL $\vert V_{\rm TH}\vert \sim 0.31$ V. Furthermore, the threshold voltage ( $V_{\rm TH})$ of the bulk FinFET can be easily tuned by varying the work function. This letter reveals that Moore’s law can continue up to 3-nm nodes.

Silicon (Si) and Germanium (Ge) ultrathin body junctionless field-effect transistor (UTB-JLFET) with $L_{G}= 1$ nm and $L_{G} = 3$ nm were demonstrated by solving the coupled drift-diffusion and density-gradient model. The simulation results show that the Si and Ge channel can be used in ultrashort channel device as long as UTB is employed. As UTB is employed, ultra-short channel device does not need to follow an empirical rule of $T_{\rm ch} = \textrm {L}_{G}/3$ . Furthermore, Ge UTB-JLFET 6T-SRAM cell has reasonable static noise margin value of 149 mV. The circuit performances reveal that UTB-JLFET can be used for sub-5-nm CMOS technology nodes.

Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length ( $\lambda $ ). This letter compares low-temperature (490 °C) MWA with high-temperature (1050 °C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage ( $\mathrm{V}_{\mathrm {\mathbf {BTBT}}}$ ) indicates clearly that TFET annealed by MWA had a lower $\lambda $ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of $10^{\mathrm {\mathbf {8}}}$ , a low subthreshold swing, and an almost negligible drain-induced barrier lowering.

Ultrathin channel trench junctionless poly-Si field-effect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness ( $T_{\mathrm {CH}})$ and gate length ( $L_{G})$ . These devices ( $L_{G}= 0.5 \mu $ m) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high $I_{\mathrm{{\scriptstyle ON}}}/ I_{\mathrm{{\scriptstyle OFF}}}$ current ratio ( $10^{6}$ A/A) and practically negligible drain-induced barrier lowering ( $\sim 0$ mV/V). The $I_{\rm \mathrm{{\scriptstyle ON}}}$ current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications.

This letter describes an asymmetric gate tunnel field-effect transistor (AG-TFET) with a gate-all-around (GAA) structure in the source and a planar structure in the drain. It has a low OFF-state current (6.55 ×10-16 A/μm) and a high ON-state current (2.47 ×10-5 A/μm) because the screening length λ of a GAA nanowire structure is half that of the planar structure. Simulations reveal that a subthreshold swing as low as 42 mV/decade and an ON/OFF current ratio as high as 1010 are realized. The AG-TFET is easily fabricated as an actual device by simply changing the layout of gate in a general TFET fabrication.

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.