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In this letter, tri-gate polycrystalline silicon variable-channel junctionless transistors (VC-JLTs), which consist of a counter-doped p-type body below an n+ active device layer, are successfully demonstrated to show a better performance compared with conventional tri-gate nanosheet (NS) JLTs. Because the potential barrier between the n-channel and p-body in the VC-JLT can be controlled by the gate, the effective conduction channel behaves as a “variable” channel, in which the conduction thickness is thinner or thicker than the physical n+ thickness for the OFF or ON state, respectively. Consequently, the VC-JLT can turn OFF more efficiently due to the enhanced volume depletion and turn ON with a smaller series resistance owing to the augmented conduction volume. In addition, for the first time, the impact of the body doping concentration is investigated and the performance sensitivities of VC-JLTs in terms of ${I}_{ \mathrm{ON}}$ , ${V}_{T}$ , S.S., and DIBL are discussed with respect to the dopant redistribution. Furthermore, the quality factor (${I}_{ \mathrm{ON}}$ /S.S.) of the VC-JLT is also benchmarked with recently published poly-Si JLTs, showing that the proposed VC-JLT exhibits good S.S. and a record ${I}_{ \mathrm{ON}}$ , which makes it as a promising device for 3-D integrated nanoelectronics. [ABSTRACT FROM AUTHOR]

In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drive stress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I\mathrm {\mathrm{{\scriptstyle ON}}} / I\mathrm {\mathrm{{\scriptstyle OFF}}} current ratio (> 107), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness ( T\mathrm {\mathbf {ch}} ) of 24 nm is 50 times smaller than conventional JL-TFT with T\mathrm {\mathbf {ch}}=12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness. [ABSTRACT FROM PUBLISHER]

In this letter, we presented theoretical results on the low-field electron mobility of ultrathin-body double-gate junctionless transistors. A 1D Poisson–Schrödinger problem perpendicular to the gate is self-consistently solved to get the electron wavefunctions, and the Kubo–Greenwood formula with consideration of phonon, surface roughness, and ionized impurity scattering is employed to evaluate the corresponding mobility components. The dependence of mobility on silicon layer thickness and doping concentration is also investigated. [ABSTRACT FROM PUBLISHER]

This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10^8 because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications. [ABSTRACT FROM PUBLISHER]

One-transistor dynamic random access memories (DRAMs) (1T-DRAMs) are considered a promising candidate to overcome the limits of scalability of conventional one-transistor/one-capacitor DRAMs. Robust and reproducible operation has been demonstrated by experiments in MOSFET devices with a gate length (L) down to \sim50 nm, which prevents their use in future technological nodes. The main factors limiting the retention time of 1T-DRAMs are the Shockley–Read–Hall recombination in the channel and the band-to-band tunneling between channel and source/drain junctions, both enhanced by the relatively high field at both junctions. In this letter, we show through statistical device simulations on a template double-gate MOSFET that, by introducing an underlap of \sim16 nm between the drain (source) junction and the gate, it is possible to reduce both the electric field at the junction and the impact of process variability, achieving 1T-DRAMs with L = \10\ \nm with a retention time in excess of 100 ms. We also show that field plates at the source and drain contacts do not provide additional advantages and that the junctionless transistor operation as 1T-DRAM is totally undermined by the impact of random dopants. [ABSTRACT FROM AUTHOR]

The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of \10^5 at W = \10 \ \nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage Vth of the JL bulk FinFET can be easily tuned by varying substrate doping concentration Nsub. The modulation range of Vth as N \rm sub changes from \10^18 to \10^19 \ \cm^-3, which is around 30%. [ABSTRACT FROM AUTHOR]

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled. [ABSTRACT FROM AUTHOR]

In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of \8 \times \10^7. Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 \mu\m exhibits a cutoff frequency (ft) of 3.36 GHz and a maximum oscillation frequency (f\max) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (Sid) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications. [ABSTRACT FROM PUBLISHER]

In this letter, we report the performance of high-\kappa /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on–off ratio (Ion/Ioff) > \10^6. For the first time, an SS lower than 70 mV/dec is achieved at LG = \13\ \nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs. [ABSTRACT FROM AUTHOR]

In this letter, we study the characteristics of n-type junctionless (JL) poly-Si thin-film transistors (TFTs) with an ultrathin and heavily phosphorous doped channel. The fabricated devices show excellent performance with a subthreshold swing of 240 mV/dec and an on/off current ratio of > \10^7. Moreover, the JL device shows 23 times increase in the on-state current at a gate overdrive of 4 V as compared with the conventional control device with an undoped channel. The significant improvement in the current drive is ascribed to the inherently high carrier concentration contained in the channel of the JL device. These results evidence the great potential of the JL poly-Si TFTs for the manufacturing of future 3-D and flat-panel electronic products. [ABSTRACT FROM PUBLISHER]

We present n-type gate-all-around (GAA) junctionless nanowire field-effect transistor (JL-NWFET) along with low-frequency noise (LFN) with respect to channel doping and the gate bias voltage. Irrespective of doping level in the channel, which is the same as that of source/drain, the JL-NWFET shows approximately five orders of magnitude lower spectral noise than the inversion-mode counterpart. LFN in JL-NWFET is also found less sensitive to gate bias voltage and to the frequency. The superior LFN behavior in GAA JL-NWFET is attributed to the conduction of carriers inside the uniformly doped nanowire channel. JL-NWFET-based sensing elements can thus be suitable in physical transducers to maximize the detection limits. [ABSTRACT FROM AUTHOR]

This letter reports on a junctionless silicon/oxide/nitride/oxide/silicon memory realized on vertical-Sinanowire gate-all-around structures with two physical storage nodes per cell. Two physical bits per cell are electrically evaluated by studying the second bit effect and the program/erase speeds, endurance, and retention. The relaxed channel length limitation due to the vertical structure provides more tolerance to overcome the scaling-related reliability issues. In addition, the absence of junctions reduces the process complexity and cost, thus making this device more manufacturable with a very low thermal budget. [ABSTRACT FROM AUTHOR]