19 results on '"Stefan Rusu"'
Search Results
2. Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC).
3. A 22 nm 15-Core Enterprise Xeon® Processor Family.
4. Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC).
5. Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).
6. Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC).
7. A 45 nm 8-Core Enterprise Xeon¯ Processor.
8. Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007).
9. A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.
10. The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.
11. A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.
12. A 400-MT/s 6.4-GB/s multiprocessor bus interface.
13. A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache.
14. Clock generation and distribution for the first IA-64 microprocessor.
15. The first IA-64 microprocessor.
16. Introduction to the Special Issue on the 34th ESSCIRC.
17. Introduction to the Special Issue on ESSCIRC'2004.
18. Guest editorial.
19. Introduction to the Special Issue on ESSCIRC 2006.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.