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This paper proposes a new space vector pulsewidth modulation (SVPWM) strategy for a hybrid input switched multilevel converter for photovoltaic energy generation systems. The converter topology is a cascaded connection of input switched and H-bridge converters, which can provide 2N + 1 voltage levels for each phase. The proposed SVPWM strategy treats the multilevel converter as a two-level converter by introducing an offset vector. With a generated switching pattern, it is possible to obtain minimum number of switching-state transitions and switch the H-bridge close to line frequency; thus, the switching losses can be significantly reduced. The proposed SVPWM strategy has been realized on a seven-level converter to demonstrate the principle of operation. The advantages of the proposed scheme and architecture are verified by both simulation and experimental results.

This paper addresses an emerging reliability and safety requirement for more electric transportation systems by proposing an on-board diagnostics plug-in tool. For this purpose, a compact diagnostic algorithm is presented using an advanced speed feedback error management technique for traction motor and generator faults which is one of the most critical parts of the vehicle powertrain. The speed measurement accuracy can be degraded for various reasons such as: sensor issues, vehicle vibration, hardware tolerances, and environmental impacts like temperature, moisture, and electromagnetic interferences. Although the speed feedback errors within an acceptable level can be tolerated by most of the drive systems, the accuracy of speed measurement is critical for the reliability of fault diagnosis. The major reason behind this fact is the frequency of fault signature in the spectrum is primarily determined using the motor speed. It is shown how the reliability of a motor fault diagnosis decision can significantly be improved under erroneous speed feedback conditions by using the developed effective error localization and coarse-to-fine detection technique. The proposed scheme is implemented through effective strategies to minimize computational complexity and memory occupancy in every step of signal processing according to manufacturers' strict cost limitation.