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A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power efficiency than delta-sigma modulation (DSM)-based randomization. Thus, a low spur level below -40 dBc is achieved with only a 4-bit phase resolution. The Class-G HR PA, including a four-level supply voltage waveform generator, is proposed as a high-efficiency and low spurious PA architecture. The proposed HR PA presents the third- and fifth-harmonics cancellation over the 0.3-to-1-GHz band, while only a single supply is required for Class-G implementation of the HR PA. The proposed BFSK TX is implemented in a 55-nm CMOS process. Measured with a 0.3-to-1-GHz continuous-wave carrier, TX output power and PA drain efficiency are 2.7 ± 0.2 dB and 52% ± 3%, respectively, operating from a 0.9-V supply. The HRs of -31.4/-42.7 and -28.2/-42.4 dBc at the third/fifth harmonics are measured at the lowest (0.3 GHz) and the highest (1 GHz) carrier frequencies, respectively. With a data rate of 1 Mb/s, the measured FSK errors are 3.6% and 4.2% at both ends of the operating frequency.

Limited by 4battery capacity, advanced microcontroller units (MCUs) for Internet of Things (IoT) applications require ultra-low power consumption. In a conventional design, the sleep power accounts for most of the total power consumption, and cannot be reduced further due to the low power efficiency of dc-dc converters at the load current ~100 nA. Voltage stacking has been proposed to address power efficiency. However, prior voltage-stacking architectures could not realize dynamic switching between flat mode and stack mode, leading to high dynamic power consumption in the normal state. This article proposes a dynamic voltage-stacking scheme, which supports two operating modes: a flat mode in the normal state and a stack mode in the sleep state. In the flat mode, the retention memories, RTC and XO32, are connected in parallel and are powered by the switched-capacitor voltage regulator (SCVR). In the stack mode, the four instances are connected in series, including the static random access memory (SRAM1) (level1), the SRAM2 (level2), and the XO32 and the RTC (level3), and the on-chip SCVR is shut down for power saving. The measurements show that compared with the conventional flat architecture, the dynamic voltage-stacking scheme reduces the sleep current by 38% under the same circumstances, and it also improves ULPMark-CP score by 23.6%, which is higher than the top1 in the ULPMark score list.

Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precisions--FP16, Hybrid-FP8 (HFP8), INT4, and INT2--to support diverse application demands for training and inference. The chip leverages cutting-edge algorithmic advances to demonstrate leading-edge power efficiency for 8-bit floating-point (FP8) training and INT4 inference without model accuracy degradation. A new HFP8 format combined with separation of the floating- and fixed-point pipelines and aggressive circuit/architecture optimization enables performance improvements while maintaining high compute utilization. A high-bandwidth ring protocol enables efficient data communication, while power management using workload-aware clock throttling maximizes performance within a given power budget. The AI chip demonstrates 3.58-TFLOPS/W peak energy efficiency and 26.2-TFLOPS peak performance for HFP8 iso-accuracy training, and 16.9-TOPS/W peak energy efficiency and 104.9-TOPS peak performance for INT4 iso-accuracy inference.

This article proposes an automotive safety integrity level (ASIL) D, which is the highest automotive integrity level specified in ISO 26262, and a target application processor for driving automation systems with a high convolutional neural network (CNN) processing performance of 60.4 trillion operations per second (TOPS) with high power efficiency of 13.8 TOPS/W. To achieve both performance and power efficiency, a stream processing architecture specialized for CNN hardware module is adopted to implement many low-power arithmetic units. In addition, 6 MB of local memories are implemented to reduce data transfers between dynamic random access memory (DRAM) and the CNN hardware, thereby improving the execution efficiency of the arithmetic units and saving power consumption caused by the data transfer. In order to support high safety integrity level with power efficiency, we provide safety mechanisms with high failure detection rates only for the hardware used in applications that require ASIL D support. The configuration of two CNN modules can switch between lockstep and single operation depending on the use case, thus achieving a tradeoff between performance and ASIL while maintaining power efficiency. In addition, the freedom from interference (FFI) concept defined in ISO 26262 is achieved by providing mechanisms to prevent low safety level tasks from interfering with high safety level tasks running concurrently inside the processor.

This work presents a 48-1V dc-dc converter with an on-chip switch and gallium nitride (GaN) hybrid power conversion. By series connecting a 12-level Dickson switched-capacitor with a two-phase switched-inductor circuit, the capacitors take over most of the 48-V voltage stresses. The circuit, thus, reduces to an equivalent 4-1V converter, making the on-chip 5-V transistor applicable for a 48-V high-voltage design. Due to the easy integration of on-chip switches and superior switch figures of merit over other 48-1V counterparts, this proposed design is able to achieve the highest switching frequency, the lowest external switch count, and the improved power density compared with other prior-state-of-the-arts. The prototype was fabricated using a 0.18-μm BCD process with an evaluation board volume of 17 mm x 15 mm x 2.6 mm. The converter achieves a maximum 8-A loading capacity with the input range from 36 to 60 V and the output from 0.5 to 1 V. The measured peak power efficiency is 90.2%, and the power density is 998 A/in³ considering the power stage volume.

This article presents a hybrid boost converter architecture for improving the efficiency of light-emitting diode (LED) drivers used in mobile applications. By cascading a low-switching frequency time-interleaved series–parallel switched-capacitor (SC)-stage with an inductive-boost converter, we facilitate lower voltage-rated switches, thus significantly reducing the switching losses. Charge-sharing losses of the SC stage are minimized by soft-charging flying capacitors with the inductor of the boost (BST) stage. Fabricated in 180-nm bipolar CMOS DMOS (BCD) process, the prototype converter generates 30-V output voltage from a Li-ion battery source. It can provide a load current in the range of 0–100 mA with an excellent peak power efficiency of 91.15% at 30 mA, which represents a 3% improvement over the state of the art.

Current retinal prostheses (RPs) have not achieved useful vision restoration, as their resolution is limited by power dissipation and complexity of interconnect. This article presents an inductively powered wireless system on a chip (SoC) for an electrically controlled, optically addressed retinal prosthetic system. The SoC interfaces to a co-fabricated nanoengineered photosensitive electrode array using only two wires. To reduce the thermal dissipation near sensitive retinal tissue, the proposed design pushes voltage regulation and charge-balanced stimulation control off the implant via a duty-cycled wireless charge metering technique. A calibration technique compensating for power fluctuation caused by eye movement is also presented. Implemented in 180-nm CMOS and delivering up to $3~\mu \text{C}$ of charge at 20-nC resolution, the SoC achieves 73% RF-to-stimulation power efficiency.

A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1–2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure consisting of 5 bit NS-SAR and 4 bit NS-SAR quantizers enables 3rd-order noise-shaping. A single operational transconductance amplifier (OTA) is shared by an integrator for noise-shaping and a residue amplifier for pipelining to maximize the power efficiency. The measured dynamic range (DR) is 84.6 dB when the sampling rate is 83.3 MS/s, bandwidth is 4 MHz, and power consumption is 3.5 mW showing Schreier figure-of-merit (FoMS,DR) of 175.2 dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer and can achieve high resolution and wide bandwidth with good power efficiency.

This article presents a hybrid single-inductor bipolar-output (SIBO) dc–dc converter for active-matrix organic light-emitting diode (AMOLED) displays, which are relatively more sensitive to the supply noise on the positive supply. First, to improve the display quality we adopt a floating negative output configuration to migrate all the switching ripples into the negative output, achieving a near-zero voltage ripple on the positive output. Second, we design low-power shunt regulators, which only deal with a small portion of the output ripple, to regulate the positive output voltage further, improving the load transient response. Besides, the hybrid topology and the proposed cross-coupled bootstrap-based level-shifter, with a dual-PMOS inverter buffer, only uses standard CMOS devices without deep-n-well, reducing the chip area and cost. The proposed converter, implemented in 0.35- $\mu \text{m}$ CMOS with 5-V devices, operates at 1 MHz, leading to a measured positive output voltage ripple lower than 1 mV (all conditions). It achieves a measured 3-mV undershoot voltage and, an unnoticeable overshoot voltage on the positive output, when the output current varies between 30 and 350 mA. The measured peak power efficiency is 89.3% at 1.1-W output power. The maximum output power is 3.5 W.

High-speed, low-power optical interconnects, such as intensity modulation direct detection (IMDD) optical links, are increasingly deployed in data centers to keep pace with the growing bandwidth requirements. High-sensitivity low-power optical receivers (RXs) are the key components that enable energy-efficient IMDD optical interconnects. This article presents a low-power nonreturn-to-zero (NRZ) optical RX using a combination of a limited-bandwidth trans-impedance amplifier (TIA) and duobinary sampling to improve RX sensitivity at high data rates. Duobinary sampling leverages the well-controlled TIA inter-symbol interference (ISI) to recover the transmitted data, making it much more hardware efficient than canceling the ISI using a decision feedback equalizer (DFE). The proposed optical RX employs a CMOS-based analog front-end (AFE) to achieve high linearity and excellent power efficiency. Fabricated in 65-nm CMOS process, the prototype RX achieves optical modulation amplitude (OMA) sensitivity of −11.6 dBm at 16 Gb/s with 0.7-pJ/bit efficiency.

This article presents an ultra-low-voltage phase-locked loop (ULVPLL) with the minimum supply voltage at 0.25 V. The offset dual-path loop architecture is proposed to relax the charge pump (CP) current matching requirement. Thus, no current mismatch suppression technique is required. This significantly mitigates the CP design challenges at such low supply voltage. In the two proposed dynamic CPs (DCPs), all the current sources, current mirrors, and op amps in the prior CPs are eliminated. Hence, the CP voltage headroom requirement is relaxed to make the DCP be suitable for sub-0.3-V operation; meanwhile, the CP power consumption and circuit design complexity are simultaneously reduced. Implemented in 40-nm CMOS with core area of 0.00873 mm2, the 0.15–1.6-GHz ULVPLL is capable of operation under a 0.25–0.4-V supply voltage. The power efficiency is 0.106 mW/GHz from 1.6-GHz output (at 0.4-V supply) and 0.048 mW/GHz from 0.2 GHz (at 0.25-V supply). Measured spur level is −58.3 dBc at 100-MHz offset from 1.6-GHz output (at 0.4-V supply) and −48.5 dBc at 12.5-MHz offset from 200-MHz output (at 0.25-V supply).

This article presents an integrated photovoltaic (PV) energy harvester for mobile applications. In the energy harvester, an irradiance-aware hybrid algorithm (IAHA) is developed to automatically select appropriate maximum power point tracking (MPPT) scheme and control methodology under different irradiance levels in order to provide high tracking efficiency and power efficiency across wide power ranges. A slew-rate-enhanced (SRE) fractional open-cell voltage (FOCV) method is also proposed to shorten the transient time for MPPT in light loads, thereby increasing energy capture from the solar panel. The proposed input-regulated boost energy harvester was developed in a 0.35- $\mu \text{m}$ CMOS process. With IAHA, the harvester achieves the MPPT efficiency >95% over an output power range from 0.65 mW to 1 W that is significantly wider than other previous state-of-the-art designs. This harvester also provides at least five times improvement in the output power range for achieving >85% power efficiency. The SRE FOCV MPPT scheme achieves a 2.9-ms MPPT transient time that reduces the prior FOCV transient time by 86 times.

This article presents a dual-output switched-capacitor (DOSC) dc–dc regulator to support hundreds-of-milliampere load per output. To save chip and board areas, the regulator adopts an all-nMOS auto-configurable power stage and generates two different output voltages via sharing flying capacitors and power transistors. In the controller, a continuous gate-drive modulation (CGDM) scheme is proposed to minimize the output cross regulation when one output undergoes large load step changes. A small output voltage ripple is also achieved at each output by the CGDM with only a small capacitance of $2.2~\mu \text{F}$ /output under heavy-load conditions. Implemented in a standard 0.13- $\mu \text{m}$ CMOS process, the proposed regulator generates two regulated outputs of 0.8 V and 1.6 V from the input of 2.7–4.2 V. It supports a maximum load of 600 mA/output, provides a low output ripple of ≤20 mV with the CGDM, and achieves a peak power efficiency of 89.5%. The output cross regulation is only 0.01 mV/mA under large load step changes of 580 mA. Compared with state-of-the-art SIMO dc–dc converters, the proposed work achieves > $4\times$ reduction in the output cross regulation under > $2\times$ larger load step changes and > $2\times$ smaller load capacitance/output.

There has been a classic design trade-off between electromagnetic interference (EMI) and power efficiency in switching power circuits historically. This work explores the technical strategies that well balance this trade-off. In particular, an emulated Miller plateau tracking scheme is proposed to identify critical di / dt and dv / dt instants, which are susceptible to load current and power input voltage conditions. An adaptive strength gate driving scheme facilitates low di / dt and high dv / dt switching operation, which leads to the targeted EMI and switching loss optimization. A switching power converter IC prototype was implemented in a 0.35- $\mu \text{m}$ high-voltage (HV) Bipolar-CMOS-DMOS (BCD) process. Operating at 10 MHz, the converter regulates an output at 5 V with 6-W power range, accommodating a wide input supply voltage ranging from 5 to 40 V. It achieves above 70% efficiency over 95.8% of the full power range, with a peak efficiency of 81.4% at 1.25 W. With the proposed strategies, the peak EMI of the converter is reduced by 19.23 dB $\mu \text{V}$ in Band B ( $\mu \text{V}$ in Band C/D (>30 MHz), with only 2.44% efficiency penalty.

This work presents a dual-band polar digital transmitter (P-DTX) based on a digitally controlled two-point edge interpolation digital-to-time converter, which is capable of supporting Wi-Fi 6 applications. The proposed P-DTX is fabricated in a standard 28-nm CMOS process. The 2.5/5GHz digital power amplifiers (DPAs) reach a maximum power ( $P_{\mathrm {MAX}}$ )/power efficiency (PE) of 27 dBm/53% and 27dBm/37%, respectively. The transmitter meets an error vector magnitude (EVM)/DPA PE/total TX power dissipation of −30.5 dB/33%/532 mW for the low band and −29 dB/26%/718 mW for the high band at 6-dB backoff (dBBO) from $P_{MAX}$ . An EVM as low as −40 dB is achieved using digital pre-distortion at 7–8 dBBO, for 20–160-MHz signal bandwidths, thus demonstrating MCS11 1024-QAM OFDM Wi-Fi 6 operation.

The bandwidth-enhanced oversampling successive approximation (BE-OSA) readout technique is proposed in this article to reduce the noise floor of the readout circuit for micro-electromechanical systems (MEMS) capacitive accelerometer while achieving high power efficiency in terms of the figure of merit (FoM). The open-loop structure has been widely used in MEMS capacitive accelerometer for the Internet of Things (IoT) applications due to its low power consumption. However, in the open-loop accelerometer, the capacitance variation in the sensing element is limited to the femto-farad level to overcome nonlinearity. As a result, the thermal noise from the parasitic capacitance becomes significant. The ability of the readout circuit to deal with thermal noise is determined by the front-end switched-capacitor capacitance-to-voltage convertor (SC CVC) rather than the back-end analog-to-digital converter (ADC). To reduce the noise floor, the traditional oversampling method increases the sampling frequency of SC CVC by increasing the transconductance of the amplifier, but this leads to low power efficiency. In this work, the BE-OSA technique provides a high power efficiency method as it increases the sampling frequency of SC CVC without increasing the transconductance of the amplifier. The SC CVC based on the BE-OSA technique is demonstrated in a readout circuit fabricated by a commercial 0.18- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process and tested with a femto-farad MEMS accelerometer. The measurement results show that compared with the readout circuit without using the BE-OSA technique, the readout circuit using BE-OSA reduces the noise floor from 2.5 to 0.9 aF/ $\surd $ Hz. Compared with other similar works, the proposed readout circuit achieves the best power efficiency in terms of both the absolute power efficiency ( $FoM_{2} =243$ fJ) among the switched-capacitor readout circuits and the relative power efficiency ( $FoM_{3} = 0.14$ ).

In this article, we demonstrate a bandpass (BP) delta–sigma modulator (DSM) using passive $N$ -path filters to implement resonators for high power efficiency, wide intermediate-frequency (IF) tuning range, and small area. The fourth-order modulator loop requires only one active element: an open-loop amplifier. The input magnitude of the amplifier is small due to the modulator’s global negative feedback and the passive $N$ -path filter preceding it. This lowers the power consumption of the amplifier and relaxes the design constraints of the switches in the $N$ -path filter. A system model of the linear periodically time-variant structure of the proposed modulator is developed, and its nonidealities are analyzed. A BP DSM prototype realized in a 65-nm CMOS with an active area of 0.032 mm2 features an IF tunable from 100 to 200 MHz with a sampling frequency ranging from 400 to 800 MHz. Over a fixed 2-MHz bandwidth, the modulator achieves a signal to noise and distortion ratio (SNDR) greater than 55.5 dB over the entire IF range. A maximal SNDR of 60.5 dB is achieved at 175-MHz IF while consuming 150 $\mu \text{W}$ , which corresponds to a Walden’s and Schreier’s figure of merits of 43.3 fJ/conv-step and 164.4 dB, respectively.

This article describes system and circuit design techniques to enhance power efficiency and incorporate new features in millimeter-wave multi-input–multi-output (MIMO) transceivers. The higher peak-to-average power ratio (PAPR) of the signal transmitted from a digital beamformer (DBF) or a fully connected hybrid beamforming (FC-HBF) transmitter compared with the conventional partially connected hybrid beamforming (PC-HBF) transmitter is identified for the first time. It is then shown that when a power amplifier (PA) with better back-off efficiency than Class-A PA is used, the overall power efficiency of the FC-HBF is superior to the PC-HBF for a given antenna geometry. Second, a new mechanism for built-in dual-band, per-element self-interference cancellation (SIC) is introduced to enable multi-antenna frequency-division-duplex (FDD) and full-duplex (FD) operation. Such SIC can only be supported in the proposed FC-HBF architecture. Several innovative circuit concepts are introduced, including low-loss wideband antenna interface design, dual-band power combining PA, dual-band RF-SIC design, and bidirectional MIMO signal path design. To demonstrate these techniques, a 28-/37-/39-GHz bidirectional two-stream front-end single-element prototype is designed in the 65-nm CMOS. The prototype can be configured as a transmit (TX) or receive (RX) element in DBFs or FC-HBFs which can in turn be configured to support TDD, FDD, or FD operation. The front-end achieves 16-/11-dB RX gain, 6.2-/7-dB NF, 15.8-/16.8-dBm saturated PA output power, and 20%/21.6% peak PA efficiency in the 28-/37-GHz bands. Extensive characterization results are presented to compare the energy efficiencies of the PC-HBF and FC-HBF architectures. The prototype is also characterized in the FDD/FD mode and achieves 36-dB peak RF-domain SIC and better than 26-dB RF-domain SIC across 0.5-GHz modulation bandwidth.

A high-efficient hybrid light-emitting diode (LED) driver is introduced in this article. By combining the merits of conventional switching-converter-based and inductor-less driving solutions, the proposed topology fully utilizes the input power from the ac mains without causing considerable switching loss or excessive voltage stress. With the help of a small-size inductor and the hybrid scheme, the proposed driver automatically alternates between switching mode and linear mode as the rectified input voltage changes. In addition, the driver can be configured either in a single stage for a high power factor (PF) and high efficiency or in the second stage of a two-stage solution for alleviating harmful low-frequency flicker. The proposed driver-integrated circuit is implemented in a 0.35- $\mu \text{m}$ high-voltage CMOS process and tested under 110-VAC 60-Hz input. Measurement results show that, when operating in the high PF configuration, the proposed driver achieves 95.1% power efficiency and 0.986 PF. For the low flicker configuration, it achieves 92% efficiency and 15% flicker while maintaining a 0.918 PF.

This article reports a power-efficient $8\times $ time-interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efficiency and conversion rate, several enhancement techniques are presented. First, a pre-defined bypass window, introduced by the customized non-binary DAC, is used to modestly reduce the power consumption. Several conversion cycles are skipped as the input signal falls within the bypass window. Second, to enhance the operation speed, two alternate comparators are adopted in each ADC channel, and an opportunistic adaptive comparator offset calibration is proposed to eliminate the conversion rate degradation caused by the dedicated calibration cycle. The comparator offset is calibrated only when the bit bypass is triggered with the calibration step size adaptively set to acquire both fast convergence and small algorithm noise. In addition, the reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without the introduction of power-hungry-distributed reference buffers. A test chip is fabricated in a 28-nm fully depleted silicon on insulator (FDSOI) process with a core area of 0.11 mm2, including the reference charge reservoirs. Clocked at 2.4 GS/s, the proposed ADC measures a 49.02-dB signal-to-noise-and-distortion ratio (SNDR) at Nyquist while consuming only 9.8 mW from a 0.9-V supply, thus resulting in Walden and Schreier figures of merit (FOMs) of 17.7 fJ/conversion-step and 159.9 dB, respectively.

We propose a simple power-efficient sub-1-V fully integrated RF front end (RFE) for 2.4-GHz transceivers. It introduces the following innovations. First, a function-reuse single-MOS digitally controlled oscillator power amplifier (DCO-PA) with full supply utilization improves antenna-to-DCO isolation for better resilience to jammers. Second, a noninverting transmitter (TX) matching transformer with a zero-shifting capacitor suppresses the second-harmonic emission of the DCO-PA and allows a single-pin antenna interface for both TX and receiver (RX) modes eliminating the transmit/receive (T/R) switches in the signal path. Third, a push–pull low-noise amplifier (LNA) reuses the TX matching transformer for passive gain boosting that reduces power consumption. Fabricated in 65-nm CMOS, the RFE occupies merely 0.17 mm2. Through the functional merge of the oscillator and PA, it can transmit 0 dBm at RF, featuring 10.2% power efficiency when delivering the RF power as low as −10 dBm at a 0.3-V supply. Under a 0.5-V supply, the LNA shows 11-dB gain and 6.8-dB noise figure (NF) while consuming 174 $\mu \text{W}$ .

This article proposes a resonant voltage mode receiver (RVM-Rx) as a new topology of a wireless power receiver for battery charging. With a resonant capacitor interleaving scheme, an LC tank in the receiver can always be configured and isolated from the output, leading to optimal power transfer regardless of the operation phase. Thus, the power transfer efficiency is not sensitive to load conditions, such as battery voltage variation. In the RVM-Rx, a diode-based voltage peak time detection (VPTD) technique enables the system operation at a high resonant frequency. Also, a delay-based control scheme with a minimum diode time tracking loop (MDTL) and an optimum duty tracking loop (ODTL) leads to efficient power conversion by adaptively adjusting the operation state. The RVM-Rx prototype in a 0.18- $\mu \text{m}$ CMOS process can operate at a high resonant frequency of 13.56 MHz with a small ${\text{R}}_{X}$ coil (7 mm $\times $ 7 mm), while achieving a maximum receiver power efficiency of 67.8% for battery charging.

This article presents a power management unit (PMU) enabling ultra-wide power-performance tradeoff well beyond voltage scaling, and adaptation to the sensed power/energy availability in the harvester and battery. Gap-less power scaling by more than five orders of magnitude and down to nW permits continuous microcontroller unit (MCU) operation regardless of the battery energy availability, thanks to a sub-mm2 on-chip harvester. Such battery-indifferent operation allows to considerably shrink the battery down, as battery discharge no longer has disruptive impact on operation. Battery-indifferent operation is enabled by introducing a purely harvested power mode in the PMU, and widely power-scalable circuits in critical blocks to maintain the power efficiency nearly constant down to nW level. To avoid pessimistic power/timing overdesign, a novel self-biasing comparator and a zero current switching scheme with fast convergence and circuit sharing across power modes are proposed. A 180-nm testchip shows MSP430-like MCU power scaling from sub-mW down to 1.85 nW, with at least 27 $\times $ power dynamic range extension compared to prior art. Self-start-up from 2-nW harvested power is demonstrated, corresponding to a 0.8-mm2 on-chip solar cell with 100-lx illuminance (i.e., equivalent to a very dark overcast day).

An ultra-low power electrocardiogram (ECG) recording front-end intended for implantable sensors is presented. The noise-limited, high power first stage of a two-stage amplifier utilizes stacking of operational transconductance amplifiers (OTAs) for noise and power efficiency improvements. The proposed technique involves upmodulated/chopped signals being applied to ac-coupled, stacked inverter-based OTAs that inherently sum the individual transconductances while reusing the same current, thereby enhancing the noise efficiency. Two prototype designs were fabricated in a 180-nm CMOS process. The three-stack version consumes 13.2 nW and occupies 0.18 mm2, whereas the five-stack implementation consumes 18.7 nW and occupies 0.24 mm2. State-of-the-art NEF and PEF metrics of less than unity, 0.86 and 0.99, respectively, are reported for the five-stack version. These correspond to ~3 $\times $ improvement in terms of energy efficiency compared to prior ultra-low power, sub-100-nW amplifiers.

A transmitter (TX)/receiver (RX) pair using galvanic coupling to achieve in-body to on-body body channel communication (I2O-BCC) for ultra-low power (ULP) miniaturized implanted applications is presented. The I2O-BCC enables low loss communication ( in vivo communication distance using the body as a transmission medium. Injection locking (IL)-based frequency-to-amplitude (F2A) conversion demodulator is proposed in RX. It can handle more than 20% frequency variations exhibited by the TX frequency-shift keying (FSK) signals due to the lack of accurate off-chip reference. The packaged implanted TX measures $7\,{\times }\,7\,{\times }\,2$ mm3. It contains a micro-battery, two micro-probes, and the designed SoC in 130-nm CMOS process. The in-body TX radio block consumes only 8.6 $\mu \text{W}$ at 500 kb/s with an on-chip power management unit that exhibits a 45% power efficiency, while the on-body RX consumes 591.5 $\mu \text{W}$ . The TX radio block power is 8 $\times $ lower than previous works and achieves energy efficiency at 17.2 pJ/b with minimal bill of material (BOM).

This article presents a fully integrated isolated power transfer system using an on-chip transformer with a magnetic core. The integrated magnetic core achieves a transformer quality factor of >12 at 20 MHz. The transformer is switched resonantly at 20 MHz using full-bridge LLC circuits to realize efficient power transfer while eliminating the excess radiated emissions with a fully symmetric topology. A multi-mode approach combining pulse width modulation (PWM) control and frequency control enables >1 W output power at an optimal power efficiency. A 5-kV galvanic isolation is achieved through thick polyimide layers between the transformer windings as well as between the windings and the core. The isolated power transfer system is packaged in a small-outline integrated circuit (SOIC) and delivers 1.1-W isolated power and achieves a peak efficiency of 52%, while passing CISPR 22 Class B radiated emissions limits with 5.8-dB margin.

With the growing demand for automotive LiDAR and the maturation of silicon photonics platforms, optical phased arrays (OPAs) have emerged as a key technology for solid-state optical beam-steering. In order to meet realistic automotive specifications with OPAs, >500 antenna elements should work reliably under tight power and cost budgets. Existing multi-chip solutions necessitate expensive packaging and assembly to achieve high interconnect density. Even with 2-D monolithic integration, high-voltage drivers to deliver sufficient power to resistive phase shifters typically result in significant overhead in die area and limited power efficiency. In this article, we introduce a single-chip OPA realized through wafer-scale 3-D integration of silicon photonics and CMOS. Flexible and ultra-dense connections with through-oxide vias (TOVs) in our platform resolve the I/O density issue. Moreover, low-voltage L-shaped phase shifters and compact, efficient switch-mode drivers, connected vertically using TOVs, remove wiring/placement overhead and achieve a large active array aperture within a compact die. Our OPA prototype achieves wide-range 2-D steering over 18.5 $^\circ \times $ 16° by leveraging wavelength tuning and phase control, and array scaling up to 125 elements with a large aperture size of $0.5\,\mathrm {mm}\times 0.5\,\mathrm {mm}$ and 0.15 $^\circ \times $ 0.25° beamwidth while consuming 20 mW/element average power. Since our system supports per-element independent phase control, increased sensitivity to process variations in L-shaped shifters is fully compensated by a simple calibration process.

A small-gate-count 8 bit bidirectional phase-domain MAC (PMAC) circuit is proposed to minimize both area and energy consumption of extremely energy-efficient deep neural network (DNN) accelerators, targeting the Internet-of-Things (IoT) edge devices operating with very strict power budgets (e.g., energy harvesting). PMAC consumes significantly less energy than standard fully digital MACs, due to its efficient analog accumulation nature based on gated-ring oscillator (GRO). The architectural analysis of energy-efficient accelerators is performed, and the energy budget analysis is disclosed. Furthermore, theoretical analysis of PMAC is conducted and comparisons with the conventional analog approaches are shown. By exploiting the DNN digital quantization noise, we further improve the PMAC energy efficiency by designing the internal gain. The bidirectional architecture proposed in this paper achieves an area comparable to those of digital MACs and up to a fivefold improvement in power efficiency. Moreover, the system design constraints are relaxed by eliminating the phase error originating in leakage currents. An asynchronous readout technique and a two-step digital-to-time converter (DTC) to enhance system throughput and compact implementation, respectively, are presented for the first time. We also present DNN hardware-software co-training procedures to show further scaling of the PMAC efficiency. Utilizing such techniques, the measured PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

To overcome the low-efficiency and limited working range of the existing RF energy harvesting (EH) systems for the wireless Internet-of-Things (IoT) sensors, a novel reconfigurable system is proposed with integrated hill-climbing, maximum power point tracking (MPPT) function for wide input power from −22 to 4 dBm. A conceptual linear model with high accuracy is also proposed to analyze the rectifier efficiency for MPPT operations. The rectifier with off-chip matching is designed with a patch antenna at 915-MHz the industrial, scientific and medical (ISM) band. To further improve the end-to-end efficiency, the harvested power is used to power up the circuit block in system on a chip (SoC) directly, avoiding additional conversion loss. Our proposed reconfigurable 12-stage rectifier with matching network achieves −18.1-dBm sensitivity for 1- $\text{M}\Omega $ loading and 36% peak efficiency at 1 dBm. The proposed MPPT function can detect and determine the optimal rectifier stage for loading from 10 $\text{K}\Omega $ to 1 $\text{M}\Omega $ . The measured MPPT accuracy is over 87% from −22 to 4 dBm compared to external tuning conditions. The minimum stand-by power is 20 nW at 0.5 V and the overall MPPT power efficiency is over 72% with a peak value of 99.8% including dissipated power. Measurements also show the system can achieve self-startup and self-sustained functions with a 10- $\mu \text{F}$ external capacitor buffer.

An ultra-low-jitter, ring- LC -hybrid injection-locked clock multiplier (ILCM) is presented to achieve a high multiplication factor of 114. The proposed hybrid ILCM cascades a ring-type voltage-controlled oscillator (VCO)-based ILCM and an LC -type VCO-based ILCM. Using a dual-purpose frequency calibrator (DPFC) that can continuously calibrate the frequency drifts of the two VCOs, concurrently, the proposed ILCM can maintain excellent jitter performance against process-voltage-temperature (PVT) variations. Since the DPFC eliminates the use of an additional calibrator and operates at a very low frequency, it can reduce the expenditures for silicon and power. The proposed ILCM was fabricated in a 65-nm CMOS process. The RMS jitter of the 22.8-GHz output, integrated from 1 kHz to 100 MHz, was 153 fs, and the DPFC restricted its variations due to variations in temperatures and supply voltages to less than 180 fs. The proposed ILCM achieved the power efficiency of 0.32 mW/GHz. The active area was 0.2 mm2. The total power consumption was 7.4 mW, but the DPFC consumed only 400 $\mu \text{W}$ .

A dual-path step-down converter (DPDC) is presented for achieving high power efficiency in the mobile power management ICs (PMICs). Adopting a hybrid structure using one inductor and one flying capacitor, the proposed DPDC supplies a load current via two parallel paths, relieved an intrinsic problem of the conventional buck converter (CBC) topology, which is a significant power loss from a large DCR of the inductor ( ${R}_{\mathrm {DCR}}$ ). Therefore, DPDC achieves a high power efficiency and thus also reduces the heating problem, which is another critical issue in the mobile set. Moreover, DPDC can shrink the volume of the PMIC set with a low manufacturing cost by alleviating an ${R}_{\mathrm {DCR}}$ specification of the inductor. In this paper, although a 250 $\text{m}\Omega $ of large ${R}_{\mathrm {DCR}}$ inductor is used for our measurements, a 96.2% of peak efficiency was achieved and the power loss of total parasitic resistances can be reduced to up to 30% of that of CBC. Moreover, according to our measurement plots, it is verified that DPDC achieves the efficiency notably higher not only in a wide load current ( $I_{\mathrm {LOAD}}$ ) range but also in a wide conversion ratio ( $V_{\mathrm {OUT}}/V_{\mathrm {IN}}$ ) range, compared to CBC.

In-ear brain–computer interface (BCI) controller system is implemented with a dedicated system-on-chip (SoC) including electroencephalography (EEG) readout and body channel communication (BCC) transceiver (TRX). The 8-mm2 chip is fabricated using 65-nm CMOS and contains three key features: 1) current reusing low-noise amplifier (CRLNA) for low power; 2) bootstrapping dc servo loop (BDSL) enabling low-noise measurement even on 350-mV electrode dc offset (EDO); and 3) dual-mode programmable gain amplifier (DMPGA) that reduces TRX power consumption by activating only when the intentional blink is present. EEG instrumentation amplifier (IA) shows the state-of-the-art 8.8 power efficiency factor (PEF) performance, and the entire integrated circuit (IC) consumes 82.9 $\mu \text{W}$ . From the measurement, with nine subjects, the proposed BCI system accomplished 84% average accuracy for the binary selection task.

This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, −3.5, −9.5, and, −13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at −13-dB PBO.

This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta–sigma modulator (CT $\Delta \Sigma \text{M}$ ). By exploiting the CCIA’s ability to block dc common-mode voltages, the bridge’s bias voltage may exceed the ROIC’s supply voltage, allowing these voltages to be independently optimized. Since bridge output is typically much smaller than bridge offset, a digital to analog converter (DAC) is used to compensate this offset before amplification and thus increase the CCIA’s useful dynamic range. Bridge loading is reduced by using a dual-path positive feedback scheme to boost the CCIA’s input impedance. Furthermore, the CCIA’s output is gated to avoid digitizing its output spikes, which would otherwise limit the ROIC’s linearity and stability. The ROIC achieves an input-referred noise density of 3.7 nV/ $\surd $ Hz, a noise efficiency factor (NEF) of 5, and a power efficiency factor (PEF) of 44, which both represent the state of the art. A pressure sensing system, built with the ROIC and a differential pressure sensor (AC4010), achieves 10.1-mPa ( $1\sigma$ ) resolution in a 0.5-ms conversion time. The ROIC dissipates about 30% of the system’s power dissipation and contributes about 6% of its noise power. To reduce the sensor’s offset drift, a temperature compensation scheme based on an external reference resistor is used. After a two-point calibration, this scheme reduces bridge offset drift by $80\times $ over a 50 °C range.

This paper presents a wide-range high-voltage (HV) isolated phase-shifted full-bridge dc–dc bus converter with eGaN power FETs driven by an integrated synchronous CMOS gate driver. The monolithic slope-sensing zero-voltage switching detector (SS-ZVSD) is developed to automatically provide adaptive deadtime control with near-constant short turn-on delay for enabling ZVS of synchronous power transistors during switching transitions under different input voltages and load currents. This not only minimizes the switching loss and the reverse conduction loss but also supports high-frequency operation, leading to high-frequency high-efficiency converters. A HV-level shifter with differential-mode noise blanking scheme is also proposed in the gate driver to enhance the converter reliability in high input voltages. To verify the performances of the isolated converter using 650-V eGaN power FETs, the gate drivers were implemented in a 1.45- $\mu \text{m}$ 700-V BCD process. The converter supports the input voltage from 150 to 400 V and delivers a maximum output power of 250 W. The proposed SS-ZVSD achieves adaptive deadtime with about 13-ns turn-on delay over wide ranges of the input voltage and load current, thereby enabling the converter running up to 2 MHz with 1.6-W power saving. The proposed converter operates 14 $\times $ faster than the prior art with comparable power efficiency.

Integrated recording of neural electrical potentials from the brain poses great challenges due to stringent dynamic range requirements to resolve small-signal amplitudes buried in noise amidst large artifact and stimulation transients, as well as stringent power and volume constraints to enable minimally invasive untethered operation. Here, we present a 16-channel neural recording system-on-chip with greater than 90-dB input dynamic range and less than 1- $\mu \text{V}_{\mathrm {rms}}$ input-referred noise from dc to 500 Hz, at 0.8- $\mu \text{W}$ power consumption, and 0.024-mm2 area per channel in a 65-nm CMOS process. Each recording channel features a hybrid analog–digital second-order oversampling analog-to-digital converter (ADC), with the biopotential signal coupling directly to the second integrator for high conversion gain and dynamic offset subtraction in the digital domain. This bypasses the need for high-pass filtering pre-amplification in neural recording systems, which often leads to signal distortion. The integrated ADC-direct neural recording offers record figure-of-merit with a noise efficiency factor (NEF) of the combined front end and ADC of 1.81, and a corresponding power efficiency factor (PEF) of 2.6. Predictive digital autoranging of the binary quantizer further supports rapid transient recovery while maintaining fully dc-coupled operation. Hence, the neural ADC is capable of recording ${\le}$ 0.01-Hz slow potentials as well as recovering from $\ge$ 200-mVpp transients within ${\le}$ 1 ms that are important prerequisites to effective electrocortical recording for brain activity mapping. In vivo recordings from marmoset primate frontal cortex demonstrate its unique capabilities in resolving ultra-slow local field potentials indicative of subject arousal state.

A power-efficient pipeline analog-to-digital converter (ADC) architecture employing a current-mode (CM) multiplying digital-to-analog converter (MDAC) is implemented in this paper. A linear operational transconductance amplifier (OTA), a current steering DAC, and a transimpedance amplifier (TIA) work together as an error amplifier to implement the first stage of the pipeline ADC. The high output impedance displayed by both OTA and MDAC allow us to maximize the power efficiency of the residue amplifier. Compared with a conventional switched-capacitor (SC) MDAC architecture, the proposed CM MDAC reduces the architecture’s power consumption. The fabricated pipeline ADC achieves a 61.3-dB/60.2-dB signal-to-noise and distortion ratio (SNDR) and a 76-dB/74-dB spurious-free dynamic range (SFDR) for a sinusoidal input of 4.15 and 97.9 MHz, respectively. The ADC’s power consumption when operating at 200 MS/s is 8.4 mW, and the conversion figure of merit (FoM) is a 44 fJ/conversion step. The prototype occupies an active area of 0.23 mm2 in a mainstream low-power 40-nm CMOS technology.

This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted output level ( $V_{\mathrm {OH}}$ ) in dynamic voltage–frequency scaling (DVFS) function, where $V_{DD}$ and $V_{DDQ}$ can be independently controlled to save system power. A two-step conversion algorithm alleviates the increase in calibration time, which is caused by an additional on-die termination (ODT) calibration for command/address (CA). The offset of a dynamic comparator in a ZQ calibration engine is averaged by a fraction-referred input switching-then-averaging (FISA) scheme which minimizes the effect of kickback noise. A code-referred periodic ZQ update (CPZU) scheme tracks the voltage and temperature variation during the background mode while minimizing the chance of malfunction by interference of both DRAM internal noise and external power noise. By applying the DVFS function based on the device usage by the user scenario in this design ( $V_{DD} =1.1$ V and $V_{DDQ} = 0.95$ V) at 1.6 Gbps, the read and the write operating power consumption can be saved by 17.7% and 18.2%, respectively, without a dynamic drop in performance. Therefore, the proposed dual-loop two-step ZQ calibration design improves the overall DRAM power efficiency based on the existing LPDDR4 SDRAM architecture without circuit overhead.

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push–pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier’s gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12 000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8 $\times $ improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

This paper presents a high-swing vertical-cavity surface-emitting laser (VCSEL) driver with two-tap feed-forward equalizer (FFE) in 14-nm FinFET CMOS technology. The design features a standby mode with power-ON time below 10 ns and 86% of power saving. Based on system-level simulations, the impact of the driver swing, tap delay, and weight on the optical eye-opening is studied and it is shown that the FFE combined with high-swing driving can improve the output eye at rates beyond two times the bandwidth of the VCSEL. By applying an extra supply, the output stage is optimized to provide high swing (0.65 V) without suffering from the slow response of a transistor in the triode region. In addition, the bias and modulation currents can be adjusted to accommodate different VCSELs. The designed circuit is tested with two VCSEL types. It is bonded to common-cathode 20 and 18 GHz VCSELs, and in both the cases, data transmission at 45 Gb/s with bit error rate lower than 10−12 is measured. The total power dissipation is below 100 mW, providing a power efficiency of better than 2.11 pJ/bit. To the best of our knowledge, this design is the fastest VCSEL driver in any CMOS technology, which is also capable of burst mode operation.

This paper presents a fully integrated buck regulator design for low-power applications. In order to enable the usage of on-chip inductor for low load current 10–40 mA, the proposed buck regulator is designed with an ultra-high switching frequency at 2 GHz, which is the highest switching frequency reported so far. To reduce the power switch losses, resonant switching scheme is utilized to save the switching clock energy. Tunable slew rate recovery circuits are used to improve the efficiency of the design. The proposed buck regulator has been implemented in 65-nm CMOS technology with a 1.1-V input. Measurement shows a wide output range of 0.3–0.86 V. The proposed design achieves up to 73% power efficiency.

This paper proposes the first feed-forward equalizing transmitter (Tx) which adaptively relaxes impedance matching. Using an on-chip time-domain reflectometer monitor, the Tx accurately detects the impedances of the channel and the receiver (Rx), and then automatically configures its termination impedance to maximize the received signal by optimally relaxing the constraint of impedance matching at the cost of a negligible penalty in signal integrity. The Tx is universally compatible with arbitrary impedances of channels and Rxs, and achieves better performance and power efficiency than the conventional Tx with impedance matching. The proposed Tx was fabricated in 65-nm CMOS technology. The Tx successfully adapted to any combination of a channel impedance of 35–75 $\Omega $ and a receiver impedance of 30–200 $\Omega $ . When the impedance matching of the Tx is adaptively and optimally relaxed, the eye size and the power efficiency are improved by up to 3.8 times and 2 times, respectively, compared with the conventional Tx. These results verify that the proposed Tx can adapt to various impedances of the channel and the receiver while achieving better performance and power efficiency than the conventional Tx with impedance matching.

This paper presents a 0.9-V 1.5-mW 150-MS/s 12-bit successive-approximation-register analog-to-digital converter (SAR ADC) in 40-nm CMOS, which achieves a synergistic integration of multi-bit per cycle (M-bit/cycle) and sub-radix techniques with the comprehensive enhancement of speed and error tolerance. The proposed sub-radix-3 architecture uses a merged digital-to-analog converter (DAC) with a two-input comparator instead of the conventional separated DACs (signal and reference DACs) with a four-input comparator to effectively improve the matching performance and the power efficiency. Alternative-reference-switching (ARS) DACs are developed to reduce the total DAC effective switching capacitance by 47.4%. Offset injection technique is implemented to calibrate the comparator offset without the speed and power penalty by eliminating the additional output loading of capacitor array or the extra input pair. The SAR logic of each conversion cycle is simplified into one single tri-latch current mode logic (CML) to directly control the DAC switches which effectively reduces the SAR delay by 2/3. The achieved peak signal to noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR), and Walden FoM are 61.7 dB, 74.4 dB, and 10.3-fJ/conversion-step, respectively.

A 50-Gb/s optical receiver (RX) based on 0.18- $\mu \text{m}$ SiGe BiCMOS technology was fabricated and evaluated. To improve the horizontal eye opening and sensitivity of the RX without degrading its power efficiency, it is configured with a two-stage pre-amplifier with high gain (56 dB $\Omega $ ) and high bandwidth (35 GHz), a high-accuracy automatic decision-threshold control (ATC) consisting of power-supply variation and offset cancellers for improving sensitivity, and a jitter-reduction packaging structure for improving transimpedance flatness. The RX achieves high sensitivity of −9.2 dBm, while its power consumption is 7.9 pJ/bit at a data rate of 50 Gb/s. In 50- and 56-Gb/s transmission tests through a 100-m multi-mode fiber (MMF), it demonstrated error-free operation at the bit error rate (BER) of less than 10–12 with the sensitivities of −9 and −6.1 dBm optical modulation amplitude (OMA). It also demonstrated 300-m error-free MMF transmission (at 50 Gb/s) with the practical sensitivity of −7.6 dBm OMA.

An auto-zero-voltage-switching (ZVS) quasi-resonant LED driver with gallium nitride (GaN) FETs for general lighting applications is presented. The proposed LED driver switches at high frequency to minimize the inductors to microhenry range. ZVS can be automatically achieved with the proposed controller to eliminate switching loss. The GaN FETs enable high-frequency operation and improve the power efficiency. A fully integrated LED shunt protector is proposed to bypass the failed LEDs in series-connected LED strings. The overall lifetime of the LED strings can be improved, and the maintenance cost can be reduced. The characteristics of the ZVS quasi-resonant LED driver with small inductors and the conditions for ZVS are also discussed in detail. The LED driver is fabricated with a 0.35- $\mu \text{m}$ 120-V high-voltage process. It can provide up to 25-W power to the LED with $2 \times 3.3\,\,\mu \text{H}$ inductors and achieves 91.4% peak efficiency and a 0.973 peak power factor from 60-Hz 100- to 120- $\text{V}_{\mathrm {ac}}$ input.

Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively.

Optical interconnects are being increasingly deployed in data centers to meet growing bandwidth requirements under tight power constraints. Therefore, there has been renewed focus on increasing data rates and improving power efficiency of optical links. Among all the link components, laser diodes typically consume the most power. Their power dissipation is dictated by the amount of signal power that needs to be transmitted to meet the bit error rate requirements under given channel loss and receiver sensitivity conditions. Consequently, improving receiver sensitivity directly helps lowering laser diode power consumption. In this paper, we present design techniques to implement such high sensitivity optical receivers. To this end, we identify noise–bandwidth tradeoffs of a shunt feedback transimpedance amplifier (SF-TIA) and elucidate how they limit the maximum achievable sensitivity at a given data rate and process technology. We then propose to combine a low-bandwidth SF-TIA with a four-tap decision feedback equalizer to overcome this noise–bandwidth tradeoff. The proposed SF-TIA uses high-gain multistage amplifier and large feedback resistance and achieves greatly improved noise performance. Fabricated in a 65-nm CMOS technology and heterogeneously integrated with a photonic IC, the proposed optical receiver achieves optical modulation amplitude sensitivity of −16.8 dBm with 1.9-pJ/bit efficiency at 12 Gb/s.

This paper presents a front-end application-specified integrated circuit (ASIC) integrated with a 2-D PZT matrix transducer that enables in-probe digitization with acceptable power dissipation for the next-generation endoscopic and catheter-based 3-D ultrasound imaging systems. To achieve power-efficient massively parallel analog-to-digital conversion (ADC) in a 2-D array, a 10-bit 30 MS/s beamforming ADC that merges the subarray beamforming and digitization functions in the charge domain is proposed. It eliminates the need for costly intermediate buffers, thus significantly reducing both power consumption and silicon area. Self-calibrated charge references are implemented in each subarray to further optimize the system-level power efficiency. High-speed datalinks are employed in combination with the subarray beamforming scheme to realize a 36-fold channel-count reduction and an aggregate output data rate of 6 Gb/s for a prototype receive array of $24 \times 6$ elements. The ASIC achieves a record power efficiency of 0.91 mW/element during receive. Its functionality has been demonstrated in both electrical and acoustic imaging experiments.

This paper presents an analog front end (AFE) that achieves a high noise efficiency by using a chopper amplifier with a 0.2-V supply inverter-based input stage followed by a 0.8-V supply stage. The high input-stage current needed to reduce the input-referred noise is drawn from the 0.2-V supply, significantly reducing power consumption. The 0.8 V stage provides high gain and signal swing, improving linearity. Biasing and common-mode rejection techniques for the ultra-low-voltage stage are presented. The AFE is implemented in a 0.18 $\mu \text{m}$ CMOS process and integrates the chopper low-noise instrumentation amplifier, a programmable-gain amplifier, and an antialiasing filter. The AFE consumes 0.79 $\mu \text{W}$ and achieves a competitive power efficiency factor (PEF) of 1.6 and an input noise of 0.94 $\mu \text{V}_{\text {rms}}$ integrated from 0.5 to 670 Hz while maintaining a 36 nV/ $\surd $ Hz input noise density down to 0.5 Hz. The included 0.8/0.2-V buck converter may be used to provide the 0.2-V supply at 72%–74% efficiency without significantly increasing noise, yielding a PEF of 1.8.

Wireless communication using terahertz/sub-terahertz band can alleviate the spectrum scarcity in conventional RF ands and satisfy the drastically expanding demands for capacity. In this paper, a spatial-orthogonal ASK transmitter architecture is presented. The self-sustaining oscillator-based transmitter architecture has an ultra-compact size and excellent power efficiency. With the proposed high-speed constant-load switch, significantly reduced modulation loss is achieved. Using polarization diversity and multi-level modulation, the throughput is largely enhanced. Array configuration is also adopted to enhance the link budget for higher signal quality and longer communication range. Fabricated in a 130-nm SiGe BiCMOS technology, the transmitter achieves an EIRP of 21 dBm and dc-to-THz-radiation efficiency of 0.7% in each spatial channel. A 24.4-Gb/s total data rate over a 10-cm communication range is demonstrated. With an external Teflon lens system, the demonstrated communication range is further extended to 52 cm. Compared with prior art, the proposed transmitter shows much higher power efficiency.