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This article presents a pitch-matched transceiver application-specific integrated circuit (ASIC) for a wearable ultrasound device intended for transfontanelle ultrasonography, which includes element-level 20-V unipolar pulsers with transmit (TX) beamforming, and receive (RX) circuitry that combines eightfold multiplexing, four-channel micro-beamforming ( $\mu $ BF), and subgroup-level digitization to achieve an initial 32-fold channel-count reduction. The $\mu $ BF is based on passive boxcar integration, merged with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering (AAF) and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link, based on 16-level pulse-amplitude modulation, concatenates the outputs of four ADCs, providing an overall 128-fold channel-count reduction. A prototype transceiver ASIC was fabricated in a 180-nm BCD technology, and interfaces with a 2-D PZT transducer array of $16\times16$ elements with a pitch of $125 ~\mu \text{m}$ and a center frequency of 9 MHz. The ASIC consumes 1.83 mW/element. The data link achieves an aggregate 3.84 Gb/s data rate with 3.3 pJ/bit energy efficiency. The ASIC’s functionality has been demonstrated through electrical, acoustic, and imaging experiments.

This article presents an application-specific integrated circuit (ASIC) for catheter-based 3-D ultrasound imaging probes. The pitch-matched design implements a comprehensive architecture with high-voltage (HV) transmitters, analog front ends, hybrid beamforming analog-to-digital converters (ADCs), and data transmission to the imaging system. To reduce the number of cables in the catheter while maintaining a small footprint per element, transmission (TX) beamforming is realized on the chip with a combination of a shift register (SR) and a row/column (R/C) approach. To explore an additional cable-count reduction in the receiver part of the design, a channel with a combination of time-division multiplexing (TDM), subarray beamforming, and multi-level pulse amplitude modulation (PAM) data transmission is also included. This achieves an 18-fold cable-count reduction and minimizes the power consumption in the catheter by a load modulation (LM) cable driver. It is further explored how common-mode interference can limit beamforming gain and a strategy to reduce its impact with local regulators is discussed. The chip was fabricated in TSMC 0.18- $\mu \text{m}$ HV BCD technology and a 2-D PZT transducer matrix of 16 $\times $ 18 elements with a pitch of 160 $\mu \text{m}$ and a center frequency of 6 MHz was manufactured on the chip. The system can generate all required TX patterns at up to 30 V, provides quick settling after the TX phase, and has an reception (RX) power consumption of only 1.12 mW/element. The functionality and operation of up to 1000 volumes/s have been demonstrated in electrical and acoustic imaging experiments.

This article presents a compact analog front-end (AFE) circuit for ultrasound receivers with linear-in-dB continuous gain control for time-gain compensation (TGC). The AFE consists of two variable-gain stages, both of which employ a novel complementary current-steering network (CCSN) as the interpolator to realize continuously variable gain. The first stage is a trans-impedance amplifier (TIA) with a hardware-sharing inverter-based input stage to save power and area. The TIA’s output couples capacitively to the second stage, which is a class-AB current amplifier (CA). The AFE is integrated into an application-specific integrated circuit (ASIC) in a 180-nm high-voltage BCD technology and assembled with a $100~\mu \text{m}$ -pitch PZT transducer array of $8\times $ 8 elements. Both electrical and acoustic measurements show that the AFE achieves a linear-in-dB gain error below ±0.4 dB within a 36-dB gain range, which is $> 2\times $ better than the prior art. Per channel, the AFE occupies 0.025 mm 2 area, consumes 0.8 mW power, and achieves an input-referred noise density of 1.31 pA / $\surd $ Hz.