Search

Describes the use of selective oxidation and ion implantation to fabricate integrated circuits. The technique of selective oxidation is used to fabricate a `walled emitter' structure as proposed by Panousis. This allows a substantial reduction in transistor size, for a given active area, over standard fabrication techniques. At the same time, parasitic device capacitances are reduced and a considerable improvement in circuit performance is realized. The impurity distribution in the various components is established by the extensive use of ion implantation. It has been demonstrated, experimentally, a 30-pJ resistor transistor-transistor logic gate fabricated using the collector diffusion isolation technology, can be fabricated in oxide isolated monolithic technology with a power-delay product of 6 pJ. Current-mode logic gates have been fabricated with a power-delay product of 1 pJ.