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This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched on and off according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at \pm 5\;\textMHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is - 35.8\;\textdBc. [ABSTRACT FROM PUBLISHER]

This paper presents a fully-integrated 3–5 GHz-band FM-UWB transmitter implemented in 90 nm bulk CMOS. The front-end consists of an RF current-controlled oscillator (RF-ICO) and class-AB power amplifier. Transmit data modulates a sub-carrier oscillator. The 2-FSK modulated output is amplified by a transconductor, and directly modulates the RF-ICO tune input. A successive approximation register (SAR) algorithm and on-chip all-digital frequency-locked loop (FLL) calibrate the carrier and sub-carrier frequencies. All voltage and current references required by the transmitter are included on-chip. The 0.2\,\times\,0.5 mm^2 active area transmitter consumes 900 \muW from a 1 V supply. Energy efficiency of the transmitter is 9 nJ/bit running continuously at 100 kbits/s. [ABSTRACT FROM AUTHOR]

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 μm CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a Δ∑ ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit. [ABSTRACT FROM AUTHOR]

A digital envelope modulator as part of a polar transmitter architecture for the 802.11a/g WLAN OFDM standards is investigated. The digital envelope modulator is quite similar to a state-of-the-art DAC design, but now it has been optimized to deal with envelope signals. A thermometer-coded envelope DAC has been implemented in a 90 nm digital CMOS process. Measurements of a test chip show the digital envelope modulator to reach an OFDM output power of -5 dBm for 54 Mb/s using 64 QAM at 2.45 GHz and fulfilling EVM specifications and in-band spectral mask requirements using just 12.7 mW from a 1.2 V supply. Combining the digital envelope modulator with an off-chip power amplifier gives an output power of 20.4 dBm, while fulfilling EVM specifications and in-band spectral mask requirements. The output power of the presented envelope DAC can be increased in a re-design by scaling device sizes. The envelope DAC is a key component in a software-defined-radio transmitter. [ABSTRACT FROM AUTHOR]