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This paper presents an impulse-radio ultra-wideband (IR-UWB) receiver design for precise wireless ranging using a newly proposed direct sampling with time-extension (DTE) method. To overcome the problems encountered in high-speed sampling for impulse signals, the DTE method, which exploits the characteristics of an impulse, is proposed. The proposed method performs high-speed sampling only during the period when short pulses exist, and quantizes the sampled signal during the dead time where no pulses exist. The high-speed impulse signal can be easily digitized using low-speed analog-to-digital converter. We designed and fabricated the IR-UWB receiver using a 65-nm CMOS process. The measurement result shows a 1.9-mm resolution for indoor wireless ranging within a 1-m range. The receiver has a power consumption of 70 mW at 1.2 V and energy efficiency of 1554 nJ/pulse.

This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time-interleaved integrating-type optical receiver, it provides 1:2 demultiplexing operation with a tolerance to lower bandwidth photodiodes. The bandwidth of current amplifier is chosen as $0.35\times $ operating data rate for maximizing the receiver signal-to-noise ratio. Experimental results show that the receiver can achieve 25 Gb/s operation when integrated with a 9 or 17 GHz GaAs photodiode. Input sensitivities in the two cases are -7.2 dBm (w/i a 9 GHz photodiode) and -10.8 dBm (w/i a 17 GHz photodiode), respectively, for a bit error rate of less than $10^{-12}$ . In addition, a single-tap decision-feedback equalizer (DFE) is embedded to compensate photodiode bandwidth and improve input sensitivity. Integrated with a low-cost 9 GHz photodiode, the input sensitivity and timing margin of the receiver are improved by 2 dB and 0.25 UI, respectively, after DFE compensation. By utilizing a current integrator and time-interleaved comparators, its energy efficiency is 1.13 pJ/b at 25 Gb/s under a 1.2 V power supply. Fabricated in a 40 nm bulk-CMOS technology, the core circuit occupies a chip area of 0.007 mm 2 only.

Large-scale multiple-input-multiple-output(MIMO) technology is drawing significant interest for the next-generation wireless networks. Traditional MIMO receiver architectures use multiple parallel receiver front ends with digitization at every element to support digital space-time array processing. The absence of analog/RF spatial interference mitigation in traditional digital MIMO receiver arrays results in a high dynamic-range requirement, and consequently, power-hungry analog and RF receiver front ends and analog-to-digital converters. This paper presents a scalable 65 nm CMOS 0.1–1.7 GHz spatio-spectral-filtering four-element MIMO receiver array with spatial notch suppression that protects the analog/RF circuits and analog-to-digital converters from spatial interference early in the signal chain. The combination of spatial and spectral filtering results in more than 19 dB rejection irrespective of the frequency at which the spatial blocker is located. The proposed spatial notch suppression technique improves the measured in-band OIP3 from –10 to +24 dBV, and the measured out-of-band IIP3 from +11 to +18 dBm. Furthermore, turning on the spatial notch suppression leads to minimal noise figure degradation. The proposed chip architecture is scalable on board without the need for RF interconnections. A wireless imaging demo shows two of the implemented integrated circuits tiled on board to form an eight-element MIMO receiver array that is able to detect a weak desired signal in the presence of an in-band 15 dB stronger spatial blocker.

A 2.4 GHz interferer-resilient wake-up receiver for ultra-low power wireless sensor nodes uses an uncertain-IF dual-conversion topology, combining a distributed multi-stage N-path filtering technique with an unlocked low-Q resonator-referred local oscillator. This structure provides narrow-band selectivity and strong immunity against interferers, while avoiding expensive external resonant components such as BAW resonators or crystals. The 65 nm CMOS receiver prototype provides a sensitivity of −97 dBm and a carrier-to-interferer ratio better than −27 dB at 5 MHz offset, for a data rate of 10 kb/s at a 10−3 bit error rate, while consuming 99 $\mu \text{W}$ from a 0.5 V voltage supply under continuous operation.

This paper presents a wideband quadrature radio receiver employing $\Delta \Sigma $ -based A/D-converting channel-select filters (ADCSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, where a first-order $\Delta \Sigma $ modulator is incorporated into a fourth-order Butterworth channel-select filter (CSF) to provide sufficient dynamic range for a cellular system. A design methodology for the ADCSF is derived, where the transfer function of the CSF is preserved. The 65 nm CMOS receiver has a frequency range of 0.6–3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.3 to 3.9 dB, with a current consumption in 2xLTE20 mode between 33 mA at 0.6 GHz and 44 mA at 3.0 GHz from a 1.2 V supply, including 10–21 mA for LO phase generation and distribution. The SNDR is 47–51 dB at an LO frequency of 1.8 GHz.

This work presents a receiver capable of receiving three simultaneous cellular channels with an aggregate bandwidth of 60 MHz, enabling a 300 Mb/s downlink rate. The receiver has 16 RF LNA ports covering the cellular bands within the 572–2700 MHz frequency range. It supports LTE-advanced Rel-12 Cat6, HSPA+ Rel-11, TD-SCDMA Rel-9, and GSM/EDGE Rel-9. The 40 nm CMOS receiver consumes 13.7 and 17.6 mA of battery current in 3G and LTE modes, respectively, including the PLL, DCXO, and biasing for a single channel.

A pulsed ultrawideband (UWB) transceiver with four-element receiver beamforming is described. Multiband signaling with frequency hopping is employed to efficiently utilize spectrum from 6 to 8.5 GHz to achieve a high data rate of 1 Gbps. A pulse-based signaling approach with low implementation complexity is utilized. Frequency-hopping reduces the overhead for multiband implementation by sharing multiple circuit blocks in the transmitter and receiver paths. The sinusoids for pulse-shaping and single-sideband mixing are synthesized using multiphase LOs to avoid high-speed DACs. The receiver channelizes the spectrum with cascaded mixers for which the LO signals are derived from a single PLL. A single-input multi-output (SIMO) beamforming architecture is employed to increase the sensitivity of the receiver. Beamforming is performed at baseband to avoid the requirement for a wideband delay circuit. The prototype is implemented in 65 nm CMOS and meets the ECC mask. The measured power dissipation of the transmitter is 221 mW, while that of the receiver is 211 mW. A receiver sensitivity of $-$ 69 dBm is achieved and Gbps communication over 2 m is demonstrated.

A software-defined radio receiver that is suitable for intra-band carrier aggregation is demonstrated. The RF front-end frequency selectivity is enhanced by the combination of the passive mixer and a proposed reconfigurable transimpedance amplifier. High order bandpass filtering function with frequency notches can be achieved at the front-end. Current domain complex signal processing is explored to select and separate multiple channels concurrently. The receiver contains a variety of functional building blocks that can be connected in different ways to form various architectures. The fine-grained programmability of component parameters and reconfigurability of receiver schemes enable optimum performance under varying signal and blocker scenarios. A proof-of-concept CMOS chip fabricated in a 65 nm CMOS technology is presented that supports up to three-channel aggregation. The receiver operates at any frequency between 0.5 to 3 GHz. The frequency separation between the concurrent RF channels can be tuned anywhere between 0 to +100 MHz. The concurrent receiver scheme can also be explored to reject large near-band blockers for high dynamic range.

Operation at millimeter-wave/sub-terahertz frequencies allows one to realize very high data-rate transceivers for wireless chip-to-chip communication. In this paper, a 240 GHz 16 Gbps QPSK receiver is demonstrated in 65 nm CMOS technology. The receiver employs a direct-conversion mixer-first architecture with an integrated slotted loop antenna. A 240 GHz LO chain drives the passive mixers to down-convert the modulated data to baseband. The baseband signal is then amplified using high gain, wide bandwidth amplifiers. The receiver has a noise figure of 15 dB with a conversion gain of 25 dB calculated from measurement data. The receiver achieves a data rate of 10 Gbps (with ${\rm BER} ) and a maximum data rate of 16 Gbps (with BER of $10^{-4}$ ) with a receiver efficiency of 16 pJ/bit.

A reconfigurable receiver that can support dual-carrier aggregation is demonstrated. Switched Capacitor (SC) technique is explored at the receiver front-end for direct RF signal conditioning. By changing the connections of the switches and capacitors, various filtering profiles, including bandpass and notch functions, can be synthesized. On the other hand, complex-domain signal processing enables RF selectivity with controllable offset frequency relative to the LO frequency. Therefore, multiple RF channels can be selected simultaneously by multiple complex-domain signal processors and a shared single front-end. The scheme also enables a 4th-order RF bandpass transfer function by combining two 2nd-order bandpass transfer functions with slightly different center frequencies. In this work, a combination of a reconfigurable front-end passive SC network and two concurrent complex-domain signal processors enables the receiver to handle different signal scenarios. A proof-of-concept CMOS chip fabricated in a 65 nm CMOS technology is presented that supports single-channel and dual-carrier aggregation receiving modes. The receiver covers the frequency range from 0.1 to 1 GHz. The frequency distance between two concurrent RF channels can be tuned anywhere between 0 to +100 MHz. The near-band blocker resilience is improved by 15 dB when the front-end is configured as a notch filter.

By employing two passive-mixer-based downconversion paths, a recently proposed noise cancelling receiver achieves a low-noise figure and tolerates most out-of-band blockers up to 0 dBm with little performance degradation. However, like most wideband passive-mixer-based designs, the architecture is far less tolerant of harmonic blockers, that is blockers located at or around precise integer multiples of the LO frequency. These blockers are problematic because they are downconverted inside the bandwidth of the baseband TIAs and, so, experience significant on-chip voltage gain. This work presents an enhanced noise-cancelling architecture that prevents harmonic blockers experiencing large on-chip gain, thereby boosting the receiver's resilience to such blockers. It will be shown that separate techniques are required for the voltage-driven main path and the current-driven auxiliary path. To validated these ideas, single-ended and fully-differential prototypes were fabricated in 28 nm silicon.

Carrier aggregation is an attractive approach to increasing the data rate in wireless communication. This paper describes an efficient carrier aggregation receiver architecture that employs one receive path and a single synthesizer. The block-downconversion scalable receiver translates all of the channels to the baseband and utilizes a new digital image rejection technique to reconstruct the signals. A receiver prototype realized in 45 nm CMOS technology along with an FPGA back end provides an image rejection ratio of at least 70 dB with a noise figure of 3.8 dB while consuming 15 mW.

A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4-3 GHz) using 8-phase passive mixers and a high-band RF path (3-6 GHz) using 4-phase passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5-50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm 2 , 28 nm CMOS receiver achieves down to 1.8 dB NF, >+3 dBm out-of-band IIP3, >70 dB calibrated HR3/5 and >+80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20-40 mW.

A software-defined radio (SDR) wireless receiver leveraging discrete-time (DT) RF signal processing is introduced. The proposed DT signal processor, which applies switched capacitor techniques to radio frequencies, achieves harmonic rejection, image rejection, and frequency translation simultaneously. A frequency tunable high-Q 2nd-order bandpass input impedance is synthesized by the DT RF signal processor, which enhances the front-end interference rejection and frequency selectivity. A proof-of-concept SDR receiver prototype, including a 65 nm LP CMOS chip and a custom designed board, is presented. The highly programmable chip allows independent control of individual block parameters and bias operating points for optimum performance under various signal scenarios. The 0.5-to-3 GHz SDR receiver achieves out-of-band IIP3 > 11 dBm, IIP2 > 46 dBm, uncalibrated 3rd and 5th order harmonic rejection exceeding 46 dB and 51 dB, respectively, and can handle up to -5 dBm blockers with less than 5 dB degradation in signal-to-noise ratio (SNR) when the blocker offset frequency is 10 times the signal bandwidth irrespective of the center frequency.

A receiver architecture suitable for coexistence applications is presented. The receiver features an auxiliary path to deflect blockers away from the main receiver without disturbing the desired received signal. The sub-2-dB noise-figure (NF) receiver addresses the coexistence blocking issues without compromising the performance, achieving comparable NF and blocker tolerance to the state-of-the-art. Implemented in 40 nm CMOS, the entire receiver including the VCO and synthesizer drains 10 mA of battery current.

An on/off keying receiver has been designed in 90 nm CMOS for low-power event-driven applications. Thanks to the synchronized-switching technique and power-efficient RF gain stages, this receiver achieves -86 dBm sensitivity (10 -3 bit error rate) at 10 kbps while consuming 123 µW from a 1 V supply. The receiver is highly scalable in data rates from 1 kbps at 64 µW to 100 kbps at 146 µW power consumption. The center frequency of the receiver can be also programmed from 780 to 950 MHz, covering different sub-GHz bands worldwide. The receiver is fully integrated, although an external SAW filter can be added for better selectivity.

A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind clock signal, which has a plesiochronous frequency-phase relation with the data. Phase alignment between the data and decision timing is achieved by interpolating the input-signal samples in the analog domain. The receiver has a continuous-time linear equalizer and a two-tap loop unrolled DFE using adjustable-threshold comparators. The receiver occupies 0.24 mm2 and consumes 308.4 mW from a 0.9-V supply when it is implemented with a 28-nm CMOS process.

The interest of industry for localization technologies is growing, because of their ability to allow a wide variety of applications. Among the different technologies, UWB is known to potentially offer the best precision. This paper presents a fully integrated low-power UWB impulse radio receiver dedicated to communication and ranging applications. The new architecture based on double quadrature is used to reach sub-cm ranging precision while limiting the speed requirements and complexity of ADC and digital signal processing. Much attention has been paid to rejecting the out-of-band signals which could degrade receiver performance while fully exploiting the available spectrum in the [3-5 GHz] band. The 5.8-mm2 0.13- μm CMOS receiver consumes 50 mW at 50-Mb/s maximum data rate. It shows -95-dBm sensitivity at 1 Mb/s and 2.5-mm maximum ranging error at 10 m.

A Bulk Acoustic Wave (BAW) resonator based 2.4-GHz low power receiver is presented in this work. The intrinsic high quality factor (Q) of the BAW resonator (around 400 at 2.4-GHz) is exploited to provide channel selection at RF and in the frequency synthesis. A novel way of addressing multiple channels (arbitrary frequency) using integer dividers and a BAW digitally controlled oscillator (DCO) and thus avoiding the need for a PLL is proposed in this work. To the best of our knowledge, this work is the first one to report a multi-channel (arbitrary frequency) receiver whose frequency synthesis depends solely on the low phase noise BAW DCO and does not include a PLL. A BAW pseudo-lattice with frequency and bandwidth tuning is proposed which significantly improves the rejection of unwanted signals in the channel filter. A quadrature sub-sampling mixer is used to down-convert the selected channel to baseband. The receiver is designed and integrated in a 0.18- μm CMOS process. With Q-boosting, the channel filter provides bandwidth down-to 1-MHz. For a BFSK modulated signal, the receiver exhibits a sensitivity of -78 \mathchar "702D dBm at a rate of 268-kbps for a BER of 10-3 . The total power consumption of the receiver is 5.94-mA from a 1.8-V power supply.

In this work we present an architecture for a low power SDR which draws on techniques from both narrowband low power radios and recent work in SDRs. The receiver consists of a wide tuning-range passive mixer, driven with resonant non-overlapping LO drive combined with a noise-power optimized multi-path baseband amplifier. LO generation circuitry drives the mixer with an 8-phase, 12.5% duty cycle LO, but does so directly from complementary LC-tank VCOs in order to resonate out the gate capacitance of the mixer. A capacitor sharing technique on the baseband side of the mixer doubles the RX frequency range of the 8-phase clock at no added cost in power or performance, while achieving a NF as low as 7 dB. The 1.8 mW low noise baseband amplifier reuses the bias current of its four input channels while rejecting the 3rd/5th harmonics by >34 dB. The receiver consumes 10–12 mW (including VCOs, pulse generation and baseband) over a frequency range of 0.7–3.2 GHz with a 1.3 V supply.

In wireless sensor nodes, using a wake-up receiver to duty-cycle the main receiver significantly reduces the overall power consumption of the node, as long as the power consumption of the always-ON wake-up receiver is very low. We demonstrate line-of-sight ultrasound data communications for ultra-low power wireless wake-up in sensor networks. The 65-nm CMOS 0.6-V receiver prototype achieves a BER of better than 10-3 measured for a 250-bps free-space 8.6-m link in an indoor environment while dissipating only 4.4 μ W and requiring only - 18 dBm electrical power to be delivered to the transmit transducer.

This paper presents a new type of wake-up receiver, called a clock-harvesting receiver, which extracts a 21 Hz clock embedded within the GSM standard for the wake-up of a wireless sensor network. The receiver was fabricated in 0.13 μm CMOS and harvests a 21 Hz clock from the 1900-MHz GSM band. It was designed for heavily duty-cycled operation to reduce the energy required for synchronization of a network. In active mode, the receiver achieves a sensitivity of -87 dBm with 57 μs of jitter while consuming 126 μW. In sleep mode, the power consumption is 81 pW. Experiments conducted in the lab verify the functionality of the receiver with a real local GSM cellular signal.

Co-existence problems in a mobile terminal environment pose strict requirements on the linearity of a front-end receiver. In this paper, active feedback is explored as a means to relax such requirements by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture addresses some of the most common problems of integrated RF filters, while maintaining their inherent tunability. Through a simplified and intuitive analysis, the operation of the receiver is examined and the design parameters affecting the filter characteristics, such as bandwidth and stop-band rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-off between noise, linearity and harmonic radiation. A prototype designed in a standard 65nm CMOS process occupies < 0:06mm2 and utilizes an RF channel-select filter with a 1-to-2:5GHz tunable center frequency to achieve 48dB of stop-band rejection and a wideband IIP3 > +12dBm.

Integrated photonics has emerged as an I/O technology that can meet the throughput demands of future many-core processors. Taking advantage of the low capacitance environment provided by monolithic integration, we developed an integrating receiver front-end built directly into a clocked comparator, achieving high sensitivity and energy-efficiency. A simple model of the receiver provides intuition on the effects of wiring and photodiode capacitance, and leads to a photodiode-splitting technique enabling improved sensitivity at higher data rates. The receiver is characterized in situ and shown to operate with μA-sensitivity at 3.5 Gb/s with a power consumption of 180 μ W (52 fJ/bit) and area of 108 μm2 . This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process.

A 1.2 V 100 Mb/s 2.93 mW discrete-time charge-domain impulse radio ultra-wideband (IR-UWB) receiver is developed in 65 nm CMOS. In the charge-domain, the template of the correlator is represented by capacitance and the correlation is implemented by charge addition instead of voltage multiplication and voltage integration. Power consumption of the charge-domain receiver is minimized by a novel auto- and cross-correlation based synchronization scheme. To reduce the power consumption and the chip area of the PLL clock generator for the receiver, a dual charge-pump PLL is proposed to scale up the capacitance of the loop filter without extra charge-pump current. The developed UWB receiver with the area- and power-efficient PLL achieves the energy consumption of 29.3 pJ/bit with the 62.5-ps timing step for data synchronization.

A quad-band 2.5G receiver is designed to replace the front-end SAW filters with on-chip bandpass filters and to integrate the LNA matching components, as well as the RF baluns. The receiver achieves a typical sensitivity of -110 dBm or better, while saving a considerable amount of BOM. Utilizing an arrangement of four baseband capacitors and MOS switches driven by 4-phase 25% duty-cycle clocks, high-Q BPF's are realized to attenuate the 0 dBm out-of-band blocker. The 65 nm CMOS SAW-less receiver integrated as a part of a 2.5G SoC, draws 55 mA from the battery, and measures an out-of-band 1 dB-compression of greater than +2 dBm. Measured as a stand-alone, as well as the baseband running in call mode in the platform level, the receiver passes the 3GPP specifications with margin.

This paper presents an 8-18 GHz wideband receiver with recursive super-heterodyne topology. A multi-feedback technology is utilized in the LNA design for the input matching over the wide frequency range in X- and Ku-band. In order to save power, both the RF and IF signals share a tunable transconductance stage. The IF output of the first mixer is fed back into the tunable input stage for IF amplification in a recursive manner, which significantly enhances the gain tuning without increasing the power. The wideband receiver MMIC is implemented in a 0.13 SiGe BiCMOS technology and achieves a 6.7-7.8 dB noise figure. The receiver average gain over the frequency range is measured as 53 dB maximum gain with 20 dB continual tuning and 36 dB discrete tuning. The average output P1dB over the frequency range is measured as 10 dBm at maximum gain. The receiver dissipates only 180 mW with a 2.2 V power supply.

Direct delta-sigma receiver architecture is introduced for wireless communication systems, such as LTE or WiMax. Architecture is based on direct downconversion, delta-sigma feedback that is up-converted to RF, and N-path filtering technique. Hence, the core receiver functions including channel selection filtering are embedded to a RF ADC with excellent linearity performance. This is achieved by transforming narrow-band filtering partially to RF injecting feedback into the input of the second amplifier stage, hence relieving requirements of the most critical subsequent stages. A 900-MHz direct delta-sigma receiver prototype occupies an active area of 1.2 mm2 in 65-nm CMOS. The receiver for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and delta-sigma modes, respectively, and out-of-band IIP3 up to +4 dBm when the delta-sigma loop is active. The chip consumes 80 mW from a 1.2-V supply.

A software-defined radio (SDR) receiver with baseband programmable RF bandpass filter (BPF) and complex impedance match is presented. The passive mixer-first architecture used here allows the impedance characteristics of the receiver's baseband circuits to be translated to the RF port of the receiver. Tuning the resistance at the baseband port allows for a real impedance match to the antenna. The addition of "complex feedback" between I and Q paths allows for matching to the imaginary component of the antenna impedance. By implementing both real and imaginary components with resistors in feedback around low noise baseband amplifiers, noise figure is also kept low. Tunable sampling capacitors on the baseband side of the passive mixer translate to tunable-Q filters on the RF port which allow for very good out-of-band linearity. Furthermore, the concept of in-band and out-of-band must be redefined as the impedance match and BPF center frequency move with the LO frequency, such that matching and filtering track the receive frequency. Additionally, 8-phase mixing is shown to provide significant benefits such as impedance matching range, rejection of blockers at LO harmonics, and lower noise figure (NF). Measurements from the receiver implemented in 65 nm CMOS show 70 dB of gain, NF as low as 3 dB, and 25 dBm out-of-band IIP3. Furthermore, tunable impedance matching shows that S11

For passive mm-wave imaging applications, broadband mm-wave receivers functioning within atmospheric windows are highly desired. Within this paper, a heterodyne receiver chipset utilizing the 140 GHz atmospheric window is presented. The heterodyne chipset is based on two different millimeter-wave monolithic integrated circuits (MIMICs). One is the receiver MIMIC including a low-noise amplifier, a down-conversion mixer, a frequency multiplier and a local oscillator buffer amplifier together with a local oscillator distribution network. The other is a voltage-controlled oscillator (VCO) working in the 35 GHz frequency range to generate the local oscillator signal for the receiver (down-converter) chip. The process technology chosen to realize the chipset is a 100 nm gatelength metamorphic InAlAs/In- GaAs high electron mobility transistor (HEMT) technology on 50 m thick and 4 inch diameter GaAs substrates. The chips are utilizing a grounded coplanar waveguide (GCPW) technology. For an operation frequency band from 120 to 145 GHz, the receiver demonstrates a flat conversion gain between -1 and +2 dB with a power consumption of 120 mW. The VCO is tuneable from 31 to 37 GHz with associated output power levels from -2 to +1 dBm. Detailed descriptions of the individual building blocks are given and measured results are presented for the building blocks as well as for the receiver.

An ultralow-power super-regenerative receiver for BFSK modulated signals has been designed and fabricated in a standard 0.18-μm CMOS process. The use of BFSK modulation allows the receiver to operate at higher data rates and also gives an approximate 3-dB SNR performance increase over the more traditional OOK modulation. A fast calibration scheme and the absence of an external inductor make it ideal for ultralow-power sensor networks. A power consumption of 215 μW from a 0.65-V supply and an area of 0.55 mm2 make it ideal for highly integrated energy harvesting sensor nodes. At 2 Mb/s, the receiver consumes 0.18 nJ/b, making it the lowest energy integrated super-regenerative receiver to date.

A dedicated wake-up receiver may be used in wireless sensor nodes to control duty cycle and reduce network latency. However, its power dissipation must be extremely low to minimize the power consumption of the overall link. This paper describes the design of a 2 GHz receiver using a novel ldquouncertain-IFrdquo architecture, which combines MEMS-based high-Q filtering and a free-running CMOS ring oscillator as the RF LO. The receiver prototype, implemented in 90 nm CMOS technology, achieves a sensitivity of -72 dBm at 100 kbps (10-3 bit error rate) while consuming just 52 muW from the 0.5 V supply.

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5deg and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.

This paper presents what kind of challenges are posed when a global positioning system (GPS) receiver is being added to a multiradio terminal. The GPS receiver chain is integrated as a part of a multiband and multimode receiver, designed for global system for mobile communications (GSM) and wideband code division multiple access (WCDMA). The hostile radio environment challenges in a terminal level are discussed. Especially, the modifications of the additional GPS mode to an existing receiver ASIC with minor and most necessary changes to the implementation is discussed and presented. The IC is implemented in a 0.13-mum CMOS technology without any analog options. At 1.2-V supply voltage and total power dissipation of 49 mW for the analog signal path, the proposed GPS receiver features a noise figure of 2.2 dB and an out-of-band IIP3 of +24 dBm for the worst-case test scenario, which makes it suitable to cellular handset usage in a demanding interference environment.

After being the subject of speculation for many years, a software-defined radio receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that in mobile handsets, it is enough to receive one channel with any bandwidth, situated in any band. Thus, the front-end can be tuned electronically. Taking a cue from a digital front-end, the receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A 90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels located anywhere from 800 MHz to 6 GHz

This paper presents an RF receiver front-end for MB-OFDM-based ultra-wideband (UWB) systems. The receiver occupies only 0.35 mm2 in a 0.18 mum CMOS process and consists of a low-noise amplifier, downconverter and a bandpass filter. There are no on-chip inductors and the receiver requires no off-chip matching components. The measured receiver gain is 21 dB, noise figure is less than 6.6 dB, input IIP3 is -5.6 dBm, and the receiver consumes 19.5 mA from a 2.3 V supply. The receiver covers all the MB-OFDM bands from 3.1 to 8 GHz.

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of -110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-mum SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.

This paper describes burst-mode receiver ICs with quick response for 1.25-Gb/s optical access networks. In a point-to-multipoint fiber access system, such as a passive optical network (PON) system, the receiver should be able to handle burst-data packets with different amplitudes. In burst-mode transmission, a receiver with a quick response is desired for high efficiency in data transmission. In addition, high sensitivity is also required for such a shared access system. To achieve a quick response and high sensitivity at the same time, a transimpedance amplifier (TIA) with three gain modes has been designed. The use of a hysteresis comparator enables fast gain mode switching. A limiting amplifier with feed-forward auto-offset compensation (AOC) is also used for quick response to burst data. These circuit techniques require no external adjustment. Using these design techniques, optical receiver ICs were fabricated in SiGe-BiCMOS technology. The optical receiver built with the ICs exhibits a settling time of under 20 bits and a sensitivity of -30 dBm with wide dynamic range of over 26 dB using a p-i-n photodiode (PD) for burst-mode optical input at 1.25 Gb/s. These fast-response receiver chips improve the data transmission efficiency. The use of a conventional p-i-n PD and the freedom from external adjustment make it possible to build an inexpensive receiver.

A 3.1-4.8 GHz ultra-wideband (UWB) receiver front-end for high data rate, short-range communication is presented. The receiver, based on the Multi Band OFDM Alliance (MBOA) standard proposal, consists of a zero-IF receive chain and an ultra-fast frequency-hopping synthesizer. The combination of high-linearity RF circuits, aggressive baseband filtering and low local oscillator spurs from the synthesizer results in an interference-robust receiver, having the ability to co-exist with systems operating in the 2.4-GHz and 5-GHz ISM bands. The packaged device shows an overall noise figure of 4.5 dB and has a measured input IP3 of -6 dBm and input IP2 of +25 dBm. Spurious tones generated by the synthesizer are below -45 dBc and -50 dBc in the 2.4-GHz and 5-GHz ISM bands, respectively. The hopping speed is well below the required 9.5 ns. The complete receive chain has been realized in a 0.25 /spl mu/m BiCMOS technology and draws 78mA from a 2.5-V supply.

This paper describes a receiver designed to meet the stringent power consumption requirements for sensor radio, which operates at 2.4-GHz ISM band with Bluetooth. To enable the reusability of the Bluetooth system, only slight changes are made in the radio parameters. The symbol rate is decreased and the increased modulation index removes the energy maximum from the channel center, which enables a low-complexity direct-conversion receiver solution. To meet the speed and power requirements, this receiver is fabricated in a 0.13-/spl mu/m CMOS process. The 3.4-mW direct-conversion demonstrator receiver includes a low-noise amplifier, which is merged with quadrature mixers, local oscillator buffers, and one analog baseband channel with a 1-bit limiter for analog-to-digital conversion. The receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.

In this paper, architecture and circuit design of a beamforming baseband receiver IC for uplink W-CDMA communication systems is presented. In the proposed receiver, a four-antenna-element beamformer and a four-finger RAKE combiner are adopted to exploit both spatial diversity and path diversity receiving. To minimize the size and power consumption of the receiver, a latch-based 1024-tap complex delay line is custom designed for the matched filter in the channel estimation circuit. The receiver chip was fabricated in a 0.35-/spl mu/m n-well CMOS single-poly quadruple-metal technology. The minimum supply voltage with the chip running at the nominal 15.36-MHz clock rate is measured at 2.15 V. The chip has an area of 6 mm by 6.3 mm and a power consumption of about 123 mW.

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.

A highly integrated direct-conversion receiver that satisfies requirements of the third-generation wide-band code-division multiple-access mobile phone standard is described. The receiver integrated circuit includes the front-end low-noise amplifier, downconversion mixers, baseband variable-gain amplifiers, channel-select filters, and the frequency synthesizer. External components are limited to matching elements required for the low-noise amplifier and the mixers and two passive band-select filters. The receiver is implemented in a SiGe BiCMOS process and consumes a total current of 46 mA from a 2.7-V supply.

A single-chip direct-conversion CMOS receiver for 2.4-GHz wide-band code-division multiple-access wireless local loop (WLL) is described. The chip includes a low noise amplifier, a 12-phase downconverter, a variable gain amplifier, a g/sub m/-C channel selection filter, a programmable phase-locked loop for seven channel frequencies, and a 4-bit flash analog-to-digital converter. The proposed multiphase reduced frequency conversion scheme combined with a multiphase sampling fractional-N prescaler, a cascaded dc-offset canceler and distributed automatic gain control loops offers solutions to problems of a direct-conversion receiver. Experimental results show -115-dBm sensitivity, 4.4-dB noise figure, and 95-dB dynamic range, which sufficiently meet commercial WLL specification.

A low-power fully integrated GSM receiver is developed in 0.35-/spl mu/m CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications.

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-/spl mu/m CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point.