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Your search keyword '"Rylov, Sergey V."' showing total 5 results
Start Over Author "Rylov, Sergey V." Journal ieee journal of solid-state circuits
5 results on '"Rylov, Sergey V."'

1. A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

Author

Proesel, Jonathan E., primary, Toprak-Deniz, Zeynep, additional, Cevrero, Alessandro, additional, Ozkaya, Ilter, additional, Kim, Seongwon, additional, Kuchta, Daniel M., additional, Lee, Sungjae, additional, Rylov, Sergey V., additional, Ainspan, Herschel, additional, Dickson, Timothy O., additional, Bulzacchelli, John F., additional, and Meghelli, Mounir, additional

Published
2018
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2. A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Author

Dickson, Timothy O., primary, Liu, Yong, additional, Rylov, Sergey V., additional, Agrawal, Ankur, additional, Kim, Seongwon, additional, Hsieh, Ping-Hsuan, additional, Bulzacchelli, John F., additional, Ferriss, Mark, additional, Ainspan, Herschel A., additional, Rylyakov, Alexander, additional, Parker, Benjamin D., additional, Beakes, Michael P., additional, Baks, Christian, additional, Shan, Lei, additional, Kwark, Young, additional, Tierno, Jose A., additional, and Friedman, Daniel J., additional

Published
2015
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3. An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

Author

Dickson, Timothy O., primary, Liu, Yong, additional, Rylov, Sergey V., additional, Dang, Bing, additional, Tsang, Cornelia K., additional, Andry, Paul S., additional, Bulzacchelli, John F., additional, Ainspan, Herschel A., additional, Gu, Xiaoxiong, additional, Turlapati, Lavanya, additional, Beakes, Michael P., additional, Parker, Benjamin D., additional, Knickerbocker, John U., additional, and Friedman, Daniel J., additional

Published
2012
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4. A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

Author

Bulzacchelli, John F., primary, Meghelli, Mounir, additional, Rylov, Sergey V., additional, Rhee, Woogeun, additional, Rylyakov, Alexander V., additional, Ainspan, Herschel A., additional, Parker, Benjamin D., additional, Beakes, Michael P., additional, Chung, Aichin, additional, Beukema, Troy J., additional, Pepeljugoski, Petar K., additional, Shan, Lei, additional, Kwark, Young H., additional, Gowda, Sudhir, additional, and Friedman, Daniel J., additional

Published
2006
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5. A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.

Author

Bulzacchelli, John F., Menolfi, Christian, Beukema, Troy J., Storaska, Daniel W., Hertle, Jürgen, Hanson, David R., Hsieh, Ping-Hsuan, Rylov, Sergey V., Furrer, Daniel, Gardellini, Daniele, Prati, Andrea, Morf, Thomas, Sharma, Vivek, Kelkar, Ram, Ainspan, Herschel A., Kelly, William R., Chieco, Leonard R., Ritter, Glenn A., Sorice, John A., and Garlett, Jon D.

Subjects
COMPLEMENTARY metal oxide semiconductors, TRANSMITTERS (Communication), RADIO transmitters & transmission, EQUALIZERS (Electronics), MOTHERBOARDS
Abstract

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28~Gb/s is 693 mW/lane. [ABSTRACT FROM PUBLISHER]

Published
2012
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