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Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write noise margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048 × 20 bit eSRAM unit is implemented in a regular 0.13 μm CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% noise margin enhancement for this scheme when a subthreshold cell is accessed. [ABSTRACT FROM AUTHOR]

Emerging high-speed lookup-intensive applications are demanding ternary content addressable memories (TCAMs) with large word-sizes, which suffer from lower search speeds due to larger match line capacitance. Therefore, low-energy high-performance design techniques are needed, which improve the search speeds of TCAMs without increasing their power consumption. In this paper, we present a cell-level comparison logic and a charge-shared match line scheme. Both schemes reduce search time and energy in TCAMs. Measurement results of the above schemes, implemented in 0.18-μm CMOS technology, show a search time reduction of 42% and 11%, and a search-energy reduction of 25 % and 9 %, respectively. [ABSTRACT FROM AUTHOR]

Embedded SRAM bit count is constantly growing limiting yield in systems-on-chip (SoCs). As technology scales into deep sub-100-nm feature sizes, the increased defect density and process spreads make stability of embedded SRAMs a major concern. This paper introduces a digitally programmable detection technique, which enables detection of SRAM cells with compromised stability [with data retention faults (DRFs) being a subset]. The technique utilizes a set of cells to modify the bitline voltage, which is applied to a cell under test (CUT). The bitline voltage is digitally programmable and can be varied in wide range, modifying the pass/fail threshold of the technique. Programmability of the detection threshold allows tracking process variations and maintaining the optimal tradeoff between test quality and test yield. The measurement results of a test chip presented in the paper demonstrate the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18 µm CMOS technology. In this paper, the design procedure of the new architecture and measurement results are reported. The delay of the DCDE changes monotonically with respect to the digital input vector. The monotonicity is one of the important features of this new architecture. Due to its monotonic behavior, the design of the DCDE is rather straightforward. The DCDE can be analyzed by a simple set of empirical equations with reasonable accuracy and can be made more tolerant to process, temperature, and supply voltage variations. The implemented delay element provides a delay resolution of as low as 2 ps and consumes 170 µW to 340 µW static power depending on the digital input vector. [ABSTRACT FROM AUTHOR]

An analytical equation for the oscillation frequency of a ring oscillator is derived. The derivation is done using a novel method which does not need to find an expression for the delay of each stage. The resulting equation includes the effect of timevarying parasitics. It also includes the effect of the gate resistance, which has a large effect on the oscillation frequency at high frequencies. Measurement results of ring oscillators fabricated in a 0.18-µm CMOS process show that the resulting equation has an average error of 8% over a large range of parameter variations. [ABSTRACT FROM AUTHOR]