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A low-power and compact CDMA matched filter has been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing single-step matching and disconnection of coupling-capacitors not involved in each matching operation. The capacitance disconnection has also enhanced the output gain to almost double. The 255-chip matched filter fabricated in a 0.35-mum CMOS technology demonstrated 5.3-mW operation at 2.5-V power supply and the chip rate of 8 Mchip/s, while occupying a chip area of 1.0 mm2

Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.

A low-power and compact code-division multiple-access (CDMA) matched filter has been developed using the switched-current technology. On-chip V-I and I-V converters featuring moderate linear characteristics have been developed for the chip. The low-power operation has been achieved by the sub-block architecture, which reduced the current flowing in current-memory cells. A low-power clock-on-demand shift register has also been developed. The 256-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated the power dissipation of 1.95 mW at the chip rate of 8 Mchip/s under 2-V power supply. The chip occupies the area of 0.54 mm/sup 2/.

A vector-quantization (VQ) processor system has been developed aiming at real-time compression of motion pictures using a 0.6-/spl mu/m triple-metal CMOS technology. The chip employs a fully parallel single-instruction, multiple-data architecture having a two-stage pipeline. Each pipeline segment consists of 19 cycles, thus enabling the execution of a single VQ operation in only 19 clock cycles. As a result, it has become possible to encode a full-color picture of 640/spl times/480 pixels in less than 33 ms, i.e., the real-time compression of moving pictures has become available. The chip is scalable up to eight-chip master-slave configuration in conducting fully parallel search for 2-K template vectors. The chip operates at 17 MHz with a power dissipation of 0.29 W under a power-supply voltage of 3.3 V.

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-/spl mu/m CMOS process. Low differential nonlinearity of less than /spl plusmn/4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 /spl mu/W per MS/s per comparator has also been achieved.

A circuit technology for self-learning neural network hardware has been developed using a high-functionality device called Neuron MOS Transistor (/spl upsi/MOS) as a key circuit element. A /spl upsi/MOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based on the charge sharing among multiple capacitors. An electronic synapse cell has been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept /spl upsi/MOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single V/sub DD/ power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making it fully compatible to the on-chip self-learning architecture of /spl upsi/MOS neural networks. The basic operation of the synapse cell and a /spl upsi/MOS neural network using the synapse has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process. >