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A low-power four-channel hybrid NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. The proposed system achieves 1 pJ/bit power efficiency, while communicating over an MDB channel with 45 dB loss at 3 GHz. The multi-tone (MT) nature of the proposed transceiver helps to control the intersymbol interference (ISI) and reduce the far-end crosstalk (FEXT), which results in a very energy-efficient implementation. The core size area is ${{80\times60\; {\upmu}\text{m}^2}}$ and {130\times60\; {\upmu}\text{m}^2} for the TX and RX blocks (including the clock unit), respectively. [ABSTRACT FROM PUBLISHER]

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 μm CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Ω resistor with an output voltage swing of VOD = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm² and the measured output jitter is σrms = 4.5 p5. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant. [ABSTRACT FROM AUTHOR]

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 µm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mmµ /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is ±3.5% and no error was detected for a 231-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value. [ABSTRACT FROM AUTHOR]