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This article presents a multimode direct radio frequency (RF) transmitter capable of a high in-band dynamic range and a low out-of-band (OOB) noise floor. It features a hybrid digital-to-analog converter (DAC) with a reconfigurable dual-band delta-sigma modulator to lower the quantization noise floor at one or two frequency bands. Additionally, a tri-level time-approximation filter is proposed to further suppress OOB noise with high tunability and stopband attenuation. The objective is to demonstrate a low-noise floor without using a surface acoustic wave (SAW) filter. For a 256-quadratic-amplitude modulation (QAM) signal with 17.4-dBm average output power at a 2.2-GHz carrier, the silicon prototype achieves -40-dB error vector magnitude (EVM) and -169-dBc/Hz noise spectral density (NSD) at 68-MHz offset by consuming a total power of 1.2 W.

The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3-σ value of the phase skew from 4.16 to 2.25 ps.

This article presents a 420-GHz phase imaging system designed in a 40-nm CMOS technology. It consists of a transmitter (TX), based on a multiplier chain, and a receiver (RX), based on a two-step IQ down-conversion. Those chips share an external, 17.5 GHz, reference to secure frequency synchronization between them. To increase the overall system signal-to-noise ratio (SNR), the TX is modulated with a low-frequency sine-wave signal, while a two-way LO power combining is implemented for the RX first mixer. Those techniques result in a measured TX effective isotropic radiated power (EIRP) of 10 dBm and RX noise figure (NF) of 27 dB, leading to the overall SNR of 52 dB (at a distance of 25 cm and a resolution bandwidth (RBW) of 100 kHz). Furthermore, the measured phase-detection root-mean-square (rms) 1σ precision is equal to 1.7° (on a 400○ range, at a distance of 25 cm and processing time of 500 ns), which leads to 3.4-μm range resolution. In addition, the system operation is illustrated in two imaging demonstrations, recognition of the printed text on paper and 3-D imaging. Those demonstrations illustrate the potential of the presented system and terahertz (THz) phase imaging in general.

This article presents a class of on-chip links that reduce energy at graceful signal quality degradation via low-swing tuning, leveraging the error resilience of prominent applications (e.g., machine learning, vision). To mitigate the exponential quality degradation at low swings, sub-word ranking and non-uniform swing allocation are introduced. An efficient swing selection to exploit local variations is presented. The proposed links also outperform approximate links in terms of energy and its variability at ISO-quality, while allowing full-quality execution when needed. The proposed techniques are demonstrated in a 28-nm testchip with differential and voltage-scaled standard CMOS links. Results on 20 dies and 3200 links under neural network (LeNet-5 and AlexNet) and computer vision workloads show that the energy can be reduced by up to 5.1X on average across 20 dies, compared with a conventionally designed link. When reusing conventional transmitter and receiver for easy integration, the minimum energy is comparable with prior best-in-class links using more advanced CMOS technologies and dedicated circuit techniques.

This article presents a full-duplex (FD) rake receiver (RX) that uses the orthogonality properties of pseudo-noise (PN) codes to reject transmitter (TX) self-interference (SI) in the RF domain, allowing simultaneous transmit and receive (STAR) operation in the same frequency channel. The rake RX also exploits multipath propagation in wireless channels and PN code orthogonality to gather signals across multipath components to increase the signal-to-noise ratio (SNR) while avoiding the fading effects of multipath channels. The rake RX shares a low-noise amplifier (LNA) between the three rake fingers and a high-linearity baseband (BB) section with the second-order filtering to improve the rejection with low power consumption. Measurements indicate that TX SI rejection is 41.2 dB in the RF domain with 9-dB SNR improvement in a multipath channel. The rake RX is implemented in a 45-nm RFSOI CMOS process and occupies an active area of 1.6 mm2 while consuming 45.8 mW per finger, including clock power consumption.

This article presents a fully integrated IEEE 802.11aj direct-conversion transceiver system in a 120-nm SiGe:C BiCMOS technology. The system includes a transmitter, a receiver, and two onboard substrates integrated waveguide-fed Yagi-Uda antennas. In the millimeter-wave frequency band, the common-mode (CM) signal in a transformer-based balun is a limiting factor for the linearity of differential devices. In this work, we analyze the cause of the CM effect and provide fast impedance equalization with a passive component compensation method to resolve this problem, which improves the linearity of the transmitter. A T-type second-order harmonic termination method is applied at the power amplifier (PA) output to further improve the linearity of the transmitter. The self-mixing method-based power detector is adopted at the output of the transmitter to have an accurate image signal and local oscillator (LO) leakage calibration. The transmitter reaches an output 1-dB compression point (OP1,dB) of 14.6-16.4 dBm and a conversion gain (CG) higher than 24 dB in the IEEE 802.11aj frequency band, operating from 42.3 to 48.4 GHz. The receiver achieves a 3.8-4.1-dB noise figure, -18.7- to -22-dBm input 1-dB compression point, and a CG better than 43.8 dB in the IEEE 802.11aj frequency band. In the system wireless data transmission test, the transceiver is fully compliant with the error vector magnitude (EVM) requirement of the IEEE 802.11aj standard up to the 64-quadrature amplitude modulation (QAM) operating mode, and the measured transmitter-to-receiver EVM is better than -28.5 dB at a 1-m distance over the IEEE 802.11aj frequency band. Compared to other states of the art, the transmitter's OP1,dB is the highest, and the demonstrated transceiver system delivers the highest performance in the IEEE 802.11aj wireless link.

This article proposes a multi-mode wireless transmitter for full-duplex (FD) and half-duplex (HD) operation based on a quadrature balanced switched-capacitor power amplifier (QB-SCPA) architecture in 65 nm CMOS. The QB-SCPA provides inherent passive transmit–receive (TX–RX) isolation along with an embedded digital self-interference cancellation (SIC) signal injection mechanism and exhibits excellent TX and RX linearity characteristics. To minimize noise figure degradation to the RX path, local oscillator (LO) signal sharing between the two SCPAs comprising the transmitter and a retiming circuit that generates the 25% clock signals is employed to obtain phase noise suppression at the LNA port. In the FD mode, 50 dB of SIC is demonstrated across the instantaneous bandwidth of a 20 MHz orthogonal frequency-division multiplexing (OFDM) signal with 11 dB peak-to-average power ratio (PAPR), along with −35 dB TX error vector magnitude (EVM) with SIC ON and without digital predistortion. The transmitter achieves a maximum output power of 23 dBm with 26.5% power-added efficiency (PAE) and 21 dBm with 17.4% PAE in HDTX and FD modes, respectively, and has a wide operating bandwidth between 1.5 and 3 GHz.

This article presents a fully integrated, wireless, RF-powered data transceiver for high-performance implants, such as neural interfaces. The design occupies a total volume of 1.6 mm3 with no need for an off-chip component. The integrated circuit (IC) receives power and downlink data with amplitude-shift-keying (ASK) modulation by an on-chip coil through an RF wireless link. For uplink data transmission, we designed a transmitter (TX) based on a power oscillator stage directly connected to an on-chip dipole antenna that supports various data rates with both on–off-keying (OOK) and ultrawideband (UWB) schemes. The radio includes a power receiver (RX) system that enables the IC to operate under various power budgets by adjusting the duty cycle of the TX. With a 25-dBm power TX at a 1-cm distance, the RX achieves a maximum data rate of 2.5 Mbps with a power consumption of 2.6 $\mu \text{W}$ . Also, the TX supports data rates of up to 150 Mbps with UWB modulation with a 15-cm operating range achieving an energy efficiency of 4.7 pJ/b. This work improves RX and TX energy inefficiencies by $\times 50$ and $\times 2.3$ , respectively.

This article presents a compact $2\times $ time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC’s architecture is based on parallel charge redistribution and separates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm2 in 16-nm CMOS and supports up to 0.32- $\textrm {V}_{\textrm {pp}}$ signal swing across its differential 100- ${\Omega }$ load. It achieves an SFDR $\geq 37$ dB and an IM $3\leq -45.6$ dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply.

We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.

This article presents a wireless multi-channel sensor interface circuit for emerging e-skin applications. The proposed interface circuit uses a CDMA-like sensing method to simultaneously record 16-channel resistive sensors and 16-channel capacitive sensors. The code-modulated multi-channel signals are conditioned and wirelessly transmitted through an edge-encoded pulsewidth-modulation ultra-wideband (PWM UWB) transmitter in the time domain. The PWM UWB transmitter eliminates the need for digitization on the sensor node, reducing the number of data to be sent. This improves the sensing and wireless transmission efficiency. With the proposed edge-encoding technique, the PWM UWB transmitter can recover the sensor data with SNR above 70 dB despite 20% data loss under a lossy environment. Fabricated in 130-nm technology, the wireless multi-channel sensor node occupies a die area of 1.35 mm2 and consumes a power of 70 $\mu \text{W}$ . It achieves an energy efficiency of 0.87 pJ/Conversion-step per channel.

This article presents an efficient quadrature digital power amplifier (DPA) based on a complex-domain Doherty (CDD) architecture. The proposed CDD architecture allows a PA to achieve high efficiency through Doherty operation in a complex domain using two independent vectors with different amplitudes and phases. It demonstrates high efficiency when two vectors have in-phase components in the complex domain by introducing an additional efficiency peak. The proposed DPA based on a switch-capacitor PA (SCPA) employs the CDD and dual-supply Class-G techniques to enhance system efficiency (SE) and adds three additional efficiency peaks down to 12-dB power back-off (PBO). An additional efficiency peak at 6-dB PBO and two additional efficiency peaks at 2.5- and 12-dB PBOs are associated with CDD and Class-G, respectively. The prototype, fabricated in a 65-nm CMOS process, achieves 27.8-dBm peak output power ( $P_{\mathrm {OUT}}$ ) with a peak SE of 32.1%. It exhibits an error vector magnitude (EVM) of −42.0 dB (−43.3 dB) at a $P_{\mathrm {OUT}}$ of 14.7 dBm (15.4 dBm) for an 802.11ax 40-MHz (20-MHz) 1024-QAM OFDM signal with 13.1-dB (12.4-dB) peak-to-average power ratio (PAPR) at 2.2 GHz. The average SE measured with a 20-MHz single-carrier 1024-QAM signal with 6.8-dB PAPR at a $P_{\mathrm {OUT}}$ of 21 dBm is 18.4%.

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) voltage-mode transmitter (TX) with a four-tap feed-forward equalizer (FFE). A two-step coarse-/fine-tuning technique is adopted in the voltage-mode FFE to reduce the number of front-end slices while maintaining sufficient resolution. In addition, the device sizes in the preceding multiplexer (MUX) and predriver can be enlarged, relaxing the self-loading effect from the layout and improving the bandwidth. An analog impedance control loop is applied to achieve output impedance matching and maintain the corresponding weighting between coarse- and fine-FFE stages. The quarter-rate 4:1 MUX incorporates an automatic phase alignment technique to eliminate the timing constraint. As a result, all of the retiming latches can be removed, saving significant power. Designed and fabricated in 40-nm CMOS, the PAM-4 TX demonstrates a high-quality eye diagram at 112 Gb/s with 3.89-pJ/b energy efficiency under a chip-on-board assembly with 5.5-dB Nyquist loss.

This article presents a 6.78-MHz wireless power transfer system with a structure-reconfigurable power amplifier (SR-PA) and a 0X/1X regulating rectifier. The proposed 0X/1X regulating rectifier with local-loop control achieves voltage rectification and regulation without dc–dc converter usage to improve the receiver efficiency. To further enhance the system efficiency, the proposed SR-PA with global-loop power control adjusts its power-stage structure to realize adaptive power delivery. The transmitter and receiver chips were fabricated in a 0.25- $\mu \text{m}$ CMOS process using 5-V devices, and the resulting system was able to regulate an output voltage of 5 V. The measurement results demonstrated an 11.2% improvement in system efficiency for a light load and a 2.7 times increase in available output power compared with the same system without transmission power control. A measured peak receiver efficiency of 92.9% and a total system efficiency of 71.5% were also demonstrated.

In this article, we present a crystal-less Bluetooth low-energy (BLE) transmitter using RF reference recovery directly from GFSK-modulated BLE packets. In order to achieve fast frequency calibration from modulated signals and reduce interference from other BLE users, the transceiver consists of a back-channel wake-up receiver, a clock-recovery receiver, a transmitter, and a dual-all-digital phase-locked loop (ADPLL) frequency synthesizer for system wake-up, clock-recovery, packet transmission, and frequency calibration. An embedded averaging processing unit in the loop filter of the ADPLL is proposed to retrieve accurate frequency information from GFSK-modulated signals. A prototype chip is fabricated in 40-nm CMOS for verification. The crystal-less transmitter with clock recovery meets all BLE requirements for SIR, making this a robust solution for removing the crystal even in densely populated networks.

This article presents a millimeter-wave (mm-wave) transmitter (TX) front-end employing a new inverse outphasing architecture with current-mode power amplifiers (PAs). This study on the conventional outphasing operation reveals its strong dependence on its voltage-mode driving source assumption and thus exhibits major limitations at mm-wave, since efficient and linear mm-wave PAs often behave as current sources. To address this challenge, we propose a current-mode inverse outphasing architecture that employs current-mode driving sources and is inherently compatible with mm-wave linear PAs. Moreover, the conventional series outphasing combiner is replaced by a much simpler and low-loss parallel power combining scheme. Closed-form mathematical expressions are derived for both the outphasing and inverse outphasing operations, including the active load modulation, Chireix compensations, and outphasing efficiency, which fundamentally explains the limitations of the conventional approach and the advantages of the inverse outphasing architecture. Further theoretical analysis discovers a circuit duality relationship between outphasing and inverse outphasing architectures, which offers unique circuit intuitions. As a proof-of-concept, we implement a 28-GHz TX front-end using cascode PAs, based on the inverse outphasing architecture. In the measurement, the TX achieves 22.7-dBm saturated output power with 42.6% PA drain efficiency. The TX exhibits effective PA efficiency enhancement at 6-dB power back-off (PBO), validating the high-efficiency inverse outphasing active load modulation. Modulation tests with high-order quadrature amplitude modulation (QAM) signals demonstrate that the TX supports >10-Gb/s high-fidelity complex signals and achieves the state-of-the-art modulation performance.

This article presents a leakage cancellation architecture for single-antenna frequency-modulated continuous-wave (FMCW) radars at W-band. A shared antenna for transmitter (TX) and receiver (RX) can substantially reduce the form factor, cost, and complexity of radar modules. Due to the simultaneous operation of the TX and RX in FMCW radars, employing a shared antenna will, however, significantly increase TX-to-RX leakage, resulting in RX saturation and desensitization. Our proposed cancellation scheme employs analog feedback to confine the TX leakage right at the RX input port, and thus, relieves the ongoing RX chain from saturation. The proposed single-antenna transceiver (TRX) prototype was fabricated in 65-nm CMOS technology with a die area of 1 mm2. The output power of 2 dBm was achieved for the TX in a frequency range of 80–84 GHz. In addition, a conversion gain and noise figure of 45 and 15 dB was measured for the RX in the presence of the TX signal via a shared antenna port. TX-to-RX isolation of more than 45 dB was achieved in the operating W-band. The chip consumes 108 mW (80.5 mW for the TX and 27.5 mW for the RX) from a 1.2-V supply voltage. Moreover, the functionality of the single-antenna radar operation was verified by connecting the chip to an on -printed circuit board (PCB) $4 \times 8$ patch antenna array with a simulated gain of 15 dBi, implemented on RO3003 Rogers material. Using the single-antenna radar module as a demo system, a $40\times 50$ cm2 rectangular metallic plate was detected at a distance up to 19 m.

An automotive 77-GHz long-range radar (LRR) with an 8-channel receiver (RX) and a 3-channel transmitter (TX) in 40-nm CMOS technology is presented. It integrates a 38.5-GHz phase-locked loop (PLL), a transmitter power detector (DET) and power calibration loop, a crystal oscillator (XO), built-in-self-test (BIST) circuits, an SRAM, an eFuse, a temperature compensation calibration loop with a lookup table (LUT) and a temperature sensor, a serial peripheral interface (SPI), and a multiple-input multiple-output (MIMO) control logic. The receiver shows a noise figure (NF) of 8.7 dB and input-referred 1-dB compression point (IP1-dB) of −7.4 dBm. The NF and IP1-dB under the worst conditions are 14 dB and −10 dBm, respectively. The transmitter shows output power of 14.1 dBm and phase noise of −116 dBc/Hz at a 12.5-MHz offset frequency, which corresponds to the frequency of 250-m objects for the fast-chirp frequency-modulated continuous wave (FMCW) radar. The proposed radar module utilizes two transmitter channels for horizontal detection. A 2 $\times $ 8 time-division-multiplexing MIMO (TDM-MIMO) technique provides a detection range of 250 m.

A single-ended four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for memory interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver with a three-point ZQ calibration scheme. This improves PAM-4 linearity by allowing the driver to compensate for its impedance variation caused by the change in the drain–source voltage ( $V_{\mathrm {DS}}$ ) to suit the four output levels considering both the TX and the receiver (RX). Resistors and inductors are eliminated from the voltage-mode (VM) driver, reducing the area requirement. The two-tap asymmetric feed-forward equalization (FFE) allocates six different coefficients to each minimum pull-up and pull-down transition, compensating for nonlinear equalization strengths and asymmetric characteristics of the driver. A prototype chip fabricated in the 65-nm CMOS has an area of 0.0333 mm2 and consumes 0.64 pJ/bit. It achieves a data rate of 28 Gb/s/pin with a ratio level separation mismatch (RLM) of 0.993.

This article presents $G$ -band monostatic and bistatic radar transceivers (TRX) incorporating on-chip antennas for short-range high-precision applications. The circuits were fabricated using a silicon–germanium (SiGe) BiCMOS technology offering heterojunction bipolar transistors (HBTs) with $\bf {f}_{\mathbf {T}}/\bf {f}_{\mathbf {MAX}}$ of 300/500 GHz. The monostatic TRX implements a tunable leakage canceller (LC) for enhanced transmitter (TX)-to-receiver (RX) leakage compensation and hence improved detectability of weakly reflecting near targets. A standalone monostatic TRX characterized at on-wafer level achieves 4-dBm maximum output power ( $\bf {P}_{\mathbf {TX}}$ ) and 19-dB peak conversion gain ( $\bf {G}_{\mathbf {RX}}$ ) with 3-dB bandwidths of 18 and 17GHz for the TX and the RX, respectively. The bistatic version reaches $\bf {P}_{\mathbf {TX}}$ of 13 dBm and $\bf {G}_{\mathbf {RX}}$ of 24 dB expanding the 3-dB bandwidths to 32 and 34 GHz for the TX and RX, respectively. A double-folded dipole antenna providing 5-dBi gain at 170 GHz was implemented using localized backside etching (LBE) and integrated with the transceivers. A frequency-modulated continuous-wave (FMCW) radar demonstrator incorporating an external phase-locked loop (PLL) was built to evaluate both TRXs and tunable leakage cancellation feature available in the monostatic variant. The maximum equivalent isotropic radiated power ( $\bf {EIRP}$ ), including on-chip antennas, is 8 and 18 dBm for the monostatic and bistatic TRX, respectively. The radars support sweep bandwidth up to 20 GHz reaching 2.1 cm spatial resolution. For a target at 1 m distance the measured ranging precision is $105~\mu \text{m}$ and $13~\mu \text{m}$ for monostatic and bistatic TRX, accordingly. Activation of leakage cancellation effectively suppresses close-in noise and extends the minimum detectable range remarkably.

This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The $LC$ PLL generates 10.25–14.5 GHz but distributes a divided version of the clock between 2.25 and 3.625 GHz with less than 140-fs integrated jitter. The local ring PLL multiplies the clock to 28 GHz but keeps the jitter less than 180 fs thanks to wide loop bandwidth. The transmitter is implemented in 7-nm FinFET consuming 175 mW with 1.56-pJ/bit efficiency.

Microring modulators (MRMs) with CMOS electronics enable compact low power transmitter solutions for 400G Ethernet and co-packaged optical transceivers. In this article, we present a 3-D-integrated 112-Gb/s pulse amplitude modulation (PAM)-4 optical transmitter (OTX) using silicon photonic MRM, on-chip laser, and co-packaged 28-nm CMOS driver. The 3- $V_{\mathrm {pp}}$ driver includes a lookup table (LUT)-based PAM-4 nonlinear equalizer to address static and dynamic MRM nonlinearities. An integrated thermal control method that is insensitive to input power fluctuations is proposed to compensate for the temperature sensitivity of MRMs. PAM-4 measurement results of our OTX at 112 Gb/s show that transmitter dispersion eye closure quaternary (TDECQ) < 1.5 dB is achieved from 28 °C to 55 °C with 7.4-pJ/bit energy efficiency including on-chip laser.

This work presents a dual-band polar digital transmitter (P-DTX) based on a digitally controlled two-point edge interpolation digital-to-time converter, which is capable of supporting Wi-Fi 6 applications. The proposed P-DTX is fabricated in a standard 28-nm CMOS process. The 2.5/5GHz digital power amplifiers (DPAs) reach a maximum power ( $P_{\mathrm {MAX}}$ )/power efficiency (PE) of 27 dBm/53% and 27dBm/37%, respectively. The transmitter meets an error vector magnitude (EVM)/DPA PE/total TX power dissipation of −30.5 dB/33%/532 mW for the low band and −29 dB/26%/718 mW for the high band at 6-dB backoff (dBBO) from $P_{MAX}$ . An EVM as low as −40 dB is achieved using digital pre-distortion at 7–8 dBBO, for 20–160-MHz signal bandwidths, thus demonstrating MCS11 1024-QAM OFDM Wi-Fi 6 operation.

This article reports a multiband frequency-division duplex (FDD) SAW-less transmitter (TX) for 5G new radio (5G-NR). It features a bandwidth-extended $N$ -path filter-modulator (BW-Ext FIL-MOD) to enable high- $Q$ bandpass filtering at a flexible RF and the synthesis of a complex-pole pair via merging positive- and negative-feedback networks (PFN/NFN) enhances its bandpass characteristic, surmounting the tradeoff between the passband flatness and out-of-band (OB) rejection, a switched-baseband (BB) input network to avoid the mutual loading effect between the BW-Ext FIL-MOD and itself, and a transimpedance amplifier (TIA)-based power-amplifier driver (PAD) to absorb both the bias and signal currents of the BW-Ext FIL-MOD for better linearity and power efficiency. Fabricated in 28-nm CMOS, the proposed TX manifests a 20-MHz passband BW and a consistently low OB noise (≤−157.5 dBc/Hz) for different 5G-NR bands between 1.4 and 2.7 GHz. The TX achieves sufficient output power (3 dBm), high TX efficiency (2.8%–3.6%), and high linearity (ACLR1 < 44 dBc and EVM < 2%). The active area is 0.31 mm2.

In this article, a body channel communication (BCC) transceiver (TRX) and low-power receiver (RX) that can cover wide applications are proposed. The IEEE 802.15.6 human body communication (HBC) physical layer (PHY) standard and high-speed data transmission are supported simultaneously with a single chip. First, the sinusoidal-modulated transmitter is proposed for the standard mode TRX, and it can reduce filtering power overhead 35%. Second, high-speed TRX is proposed that can support dual-band QPSK modulation to increase system data rate and bandwidth efficiency. Third, on-chip RC duplexer is proposed for full-duplex function in communication. Also, for the low-power RX, a wireless power transfer (WPT)-based wake-up receiver (WuRX) and a higher energy efficiency main RX is integrated into RX chip. The main HBC RX demodulates both ASK and frequency-shift keying (FSK) information with a sharing oscillator (OSC) with 31- $\mu \text{W}$ low-power consumption. The TRX and RX are implemented in 65-nm CMOS process.

This article presents a 390-GHz outphasing transmitter in 28-nm CMOS. Generating higher order modulation schemes at terahertz (THz) frequencies is very challenging due to the essential nonlinear elements needed to generate signals above Fmax. Harmonic outphasing could provide an answer for transmitters which use a multiplier last topology. The topology addresses both amplitude and phase distortion issues, which are inherent for multiplier-last architectures. The 5-bit on-chip outphasing symbol generator is sufficient to generate modulation schemes from OOK to 16-STAR QAM. The chip is packaged with a direct chip-to-waveguide interface thus providing easy RF access through the WR2.2 waveguide interface. The transmitter can deliver a peak measured output power of −16 dBm with a 3-dB IF bandwidth of 16.5 GHz. The maximum achieved data rate was 6 Gb/s.

We developed a 300-GHz-band 120-Gb/s wireless transceiver front-ends (TRX) using our in-house InP-based high-electron-mobility-transistor (InP-HEMT) technology for beyond-5G. The TRX is composed of the RF power amplifiers (PAs), mixers, and local oscillation (LO) PAs which are all packaged in individual waveguide (WG) modules by using a ridge coupler for low-loss WG-to-IC transition. RF PAs are designed using the low-impedance inter-stage-matching technique to reduce the inter-stage matching loss of the amplifier stages, and the back-side DC line (BDCL) technique is used to simplify the layout and to improve the gain of the PAs. The fabricated RF PAs show a high output 1-dB compression point of more than 6 dBm from 278 to 302 GHz. The mixers are used for both up- and down-conversion in the transmitter and receiver. These mixers are designed to have high conversion gain (CG) over the wideband even after packaging by enhancing the isolation between the RF and IF ports. The measured CG of mixer module is −15 dB, and the 3-dB IF-bandwidth is 32 GHz. The LO PAs are also designed using the BDCL technique so that they can supply the required LO power to the mixers. The TRX with these InP building blocks enables the data transmission of a 120 Gb/s 16QAM signal over a link distance of 9.8 m.