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This paper presents a single-inductor triple-source quad-mode (SITSQM) energy-harvesting interface in a 0.18- $\mu \text{m}$ CMOS process. The proposed reversely polarized energy recycling (RPER) technique improves not only the conversion efficiency at low input voltage but also the system’s output power range. The interface employs the buck–boost topology to convert energy from photovoltaic (PV) cells and a thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter features four different operating modes, namely, harvesting, recycling, storing, and backup. The operating mode is automatically selected according to the input and load conditions using the automatic source selection mechanism. The experimental results demonstrate 25.3% efficiency improvement and 10 $\times $ output power range extension from the proposed RPER technique. The proposed SITSQM converter automatically manages three harvesting sources with 82.1% peak conversion efficiency.

We propose an algorithmic voltage-feed-in (AVFI) topology capable of systematic generation of any arbitrary buck–boost rational ratio with optimal conduction loss while achieving reduced topology-level parasitic loss among the state-of-the-art works. By disengaging the existing topology-level restrictions, we develop a cell-level implementation using the extracted Dickson cell (DSC) and charge-path-folding cell (QFC) to minimize the power-stage parasitic loss, exhibiting a Dickson-like switching pattern. The proposed partitionable main cell (MC) and auxiliary cell (AC) architecture achieves fined-grained voltage conversion ratio (FVCR) reconfiguration with optimal power cell utilization and reduced control complexity. Implemented in 65-nm bulk CMOS, the fully integrated switched-capacitor power converter (SCPC) using 10 MCs and 10 ACs executes a total of 24 VCRs (11 buck and 13 boost) with wide-range efficient buck–boost operations through the proposed reference-selective bootstrapping driver (RSBD). Based on the AVFI topology, the chip prototype reaches a measured peak efficiency of 84.1% at a power density of 13.4 mW/mm2 over a wide range of input (0.22–2.4 V) and output (0.85–1.2 V).

In this paper, we present a single-inductor triple-input–triple-output (SITITO) buck–boost converter in a 0.18- $\mu \text{m}$ CMOS process for dual-source energy harvesting. The converter operates in the single-source mode, dual-source mode (DSM), and backup mode automatically by detecting the input and output conditions. Converter operation in the proposed DSM enables extraction of power from both a photovoltaic cell and a thermoelectric generator in one switching cycle for efficient power extraction. The cycle-by-cycle source-tracking approach selects the appropriate input source according to the maximum power point of the energy transducers. The adaptive on-time circuit with the proposed adaptive peak-inductor-current (APIC) control adjusts the on-time of power transistors to obtain high conversion efficiency under different input voltages. The experimental results demonstrate that the proposed SITITO converter has a peak efficiency of 84.4%. When compared with the conventional constant peak-inductor-current control, an efficiency improvement of 11% is obtained via the proposed APIC control.

A mixed-ripple adaptive on-time controlled boost converter is proposed. With the proposed control method, the compensator network is no longer required. Hence, the chip area and cost can be reduced, and a satisfied load regulation still can be achieved. Besides, a novel on-time generator is proposed to fix the switching frequency in continuous conduction mode (CCM). Moreover, a differential difference comparator is proposed to simplify the circuits and further reduce chip area. Furthermore, with the proposed control, the converter is capable of smoothly switching between discontinuous conduction mode and CCM, depending on the loading condition. The proposed boost converter was implemented by using a 0.18- $\mu \text{m}$ 1P6M mixed-signal process, and the chip area is 0.88 mm2. The input voltage may range from 0.8 to 1.4 V, the output voltage is set to 1.8 V, and the measured peak efficiency is 92.4%.

This paper presents a 50-MHz 5-V-input 3-W-output three-level buck converter. A real-time flying capacitor ( $C_{F}$ ) calibration is proposed to ensure a constant voltage of $V_{g}$ /2 across $C_{F}$ , which is highly dependent on various practical conditions, such as parasitic capacitance, time mismatches, or any loading circuits from $C_{F}$ . The calibration is essential to ensure the reliability and minimize the inductor current and output voltage ripple, thus maintaining the advantages of the three-level operation and further extending the system bandwidth without encountering sub-harmonic oscillation. The converter is fabricated in a UMC 65-nm process using standard 2.5-V I/O devices, and is able to handle a 5-V input voltage and provide a 0.6–4.2-V-wide output range. In the measurement, the voltage across $C_{F}$ is always calibrated to $V_{g}$ /2 under various conditions to release the voltage stress on the high- and low-side power transistors and $C_{F}$ , and to ensure reliability with up to 69% output voltage ripple reduction. A 90% peak efficiency and a 23–29-ns/V reference-tracking response are also observed.

A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The dc–dc converter achieves 93% peak efficiency for $V_{i}= 2$ V and $V_{o}= 1.6$ V.

An efficient buck/buck-boost reconfigurable LED driver based on peak current control is introduced. The driver supports pulse-width modulation (PWM) and pulse-frequency modulation (PFM) operations. The use of a combination of rectified sin and sin2 functions in the reference is introduced for the purpose of improving the power factor (PF) and total harmonic distortion (THD) of buck and buck-boost converters. The optimal reference waveform shape for buck and buck/boost modes can be set externally. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different ac line voltages. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and the peak PF and lowest THD values are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), and buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.

This paper presents a digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) dc-dc converter with low output voltage ripple and high efficiency. To achieve wide input and output voltage ranges, six voltage conversion ratios are generated with only two discrete flying capacitors by using both 2- and 3-phase operations. An adaptive ripple reduction scheme is proposed to achieve up to four times reduction in the output voltage ripple. The complexity of controller design is reduced by using digital synthesis, and the technique is scalable with process. Fast loop response is achieved by using synchronized hysteretic control. The SC converter was fabricated in a 0.13- $\mu \text{m}$ CMOS process. It can deliver a maximum power of 250 mW to an output of 0.5–3 V with a wide input voltage range of 1.6–3.3 V. Compared to an SC converter with only 2-phase operation, the maximum efficiency improvement is 20%. The converter achieves a peak efficiency of 91%.

A fully integrated step-down switched-capacitor dc–dc converter ring with 123 phases has been designed that could achieve fast dynamic voltage scaling for the microprocessor of wearable devices. The symmetrical multiphase converter ring surrounds its load in the square and supplies power to the on-chip power grid that is easily accessible at any point of the chip edges. The frequency of the $V_{\mathrm {DD}}$ -controlled oscillator is adjusted through its supply voltage $V_{\mathrm {DD}}$ , which allows the unity-gain frequency to be designed higher than the switching frequency. The converter ring has been fabricated in a low-leakage 65-nm CMOS process. This converter achieves a response time of 3 ns, a reference tracking speed of 2.5 V/ $\mu \text{s}$ , and a minimum output ripple of 2.2 mV. The peak efficiency is 80% at the power density of 66.6 mW/mm2, and the maximum power density is 180 mW/mm2.

This paper presents a hybrid supply modulator (SM) with a comprehensive analysis of receiver (RX) band noise in an envelope tracking power amplifier (ET-PA). The designed SM supports both ET mode and average power tracking (APT) mode depending on the PA output power level. In the APT mode, an integrated buck-boost (BB) converter with hysteretic control generates dc supply voltage and its average switching frequency ranges from 1 to 2 MHz. In the ET mode, the bandwidth of SM is determined by a linear amplifier, which has about 30 MHz of signal bandwidth. To improve the ET efficiency, an ac coupling capacitor, with an adaptive offset control, and scaled linear supply are used. The scaled linear supply is provided by the BB converter. To lower the output noise of the SM, a parallel class-AB output buffer and resonance frequency tuning schemes are applied in this paper. For long term evolution 10 MHz with quadrature phase shift keying modulation and 5.8 dB peak-to-average power ratio, the designed SM achieves 82% efficiency at 800 mW output power with a fixed 8 $\Omega $ resistor. Adapting the proposed SM to a PA, a 10 dB ET operation dynamic range is achieved while achieving a power added efficiency of 42.6% at 27 dBm PA output power. The measured SM output noise is −137 dBm/Hz at 95 MHz offset with the PA load, and the PA RX band noise is −124 dBm/Hz, which is dominated by the stand-alone PA itself. The chip is implemented with a 130 nm CMOS process and the die size is 5.0 mm2.

A DC-DC converter, which tracks minimum power loss under various conditions, is presented in this paper. With this DC-DC converter, a new approach for optimum efficiency, which implements theoretical equations intactly at the circuit level, was adopted. This approach has high reliability against process variation. The concept of lossless soft-switching was also adopted in discontinuous-conduction-mode (DCM) operation. The proposed DC-DC converter has a maximum power efficiency of 91% at the switching frequency of 1 MHz. The proposed converter is able to maintain a maximum power efficiency of around 90% over the whole range of input voltage from 2.9 to 4.5 V and output voltage from $-$ 3.8 to $-$ 5.9 V. This chip is implemented in a 0.35 $\mu$ m BCD process and occupies an area of 2.1 $\times $ 1.4 mm $ ^{2}$ .

Mobile devices need to minimize their power consumption in order to maximize battery runtime, except during short extremely busy periods. This requirement makes dc-dc converters usually operate in standby mode or under light-load conditions. Therefore, implementation of an efficient regulation scheme under a light load is a key aspect of dc-dc converter design. This paper presents a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control. The converter includes four phases operating in an interleaved manner in order to supply high current with low output ripple. The multiphase converter implements a rotating phase-shedding scheme to distribute the switching activity concentrated on a single phase, resulting in a distribution of the aging effects among the phases instead of a single phase. The proposed multiphase buck converter was fabricated using a 0.18 μm bipolar CMOS DMOS process. The supply voltage ranges from 2.7 V to 5 V, and the maximum allowable output current is 4.5 A.

This paper presents an 80 mV startup-voltage dual-mode boost converter for energy harvesting applications. The charge-pumped pulse generator enables a startup operation of the boost converter from the input voltage of 80 mV. The threshold voltage tuned oscillator for the clock generator of the boost converter compensates for the die-to-die process variation by a hot carrier injection (HCI), thereby reducing the minimum operation voltage (VDDMIN) of the clock generator by 45% with a trimming time of 10 minutes. The proposed step-up converter achieves the lowest startup voltage without using a mechanical switch or a large transformer.

This paper presents a spurious-free switching buck converter with enhanced light-load efficiency for use in noise-sensitive portable electronics. The proposed switching buck converter achieves low output noise by using a delta-sigma-modulator (ΔΣ) controller. Its light-load efficiency is enhanced by: 1) scaling the switching frequency of the buck converter (i.e., the sampling frequency of its ΔΣ-modulator controller) with the load current; 2) switching its operation from continuous conduction mode (CCM) to discontinuous conduction mode (DCM) at light loads; and 3) using a new low-power current-sensing circuit. The ΔΣ modulator is designed with an input-feedforward architecture, which enables the switching frequency of the controller to be scaled without disturbing the stability of the feedback loop of the buck converter, and also reduces the controller quiescent current. The proposed switching buck converter was fabricated in 0.13-μm digital CMOS. Measurements results demonstrate that this buck converter achieves a spurious-free output with a noise floor below -60 dBm and voltage ripples below 70 mV over its full loading range (2 mA to 800 mA). Furthermore, it achieves a power efficiency higher than 70% over this entire range, with a peak efficiency of 95.1%.

On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range of output voltages compared to a 1/2 mode switched-capacitor converter. The test-chip prototype delivers up to 0.85 A load current while generating output voltages from 0.4 to 1.4 V from a 2.4 V input supply. It achieves 77% peak efficiency at power density of 0.1 W/mm2 and 63% efficiency at maximum power density of 0.3 W/mm2. The converter scales output voltage from 0.4 V to 1.4 V (or vice-versa) within 20 ns at a constant 450 mA load current. A shunt regulator reduces peak-to-peak voltage noise from 0.27 V to 0.19 V under pseudo-randomly fluctuating load currents. Using simulations across a wide range of design parameters, the paper compares conversion efficiencies of the 3-level, buck and switched-capacitor converters.

This paper presents circuit techniques to improve the efficiency of high-current LED drivers. An error-averaged, senseFET-based current sensing technique is used to regulate the LED current accurately. Because the proposed scheme eliminates the series current-regulation element present in all conventional LED drivers, it greatly improves efficiency and reduces cost. The converter operates in three different operating modes, namely buck, buck-boost, and boost modes, and achieves high efficiency over the entire Li-Ion battery range (3-5.5 V). Fabricated in 0.5-μm CMOS process, the prototype occupies an active area of 5 mm2. At 1.2-A LED current, the driver achieves an efficiency improvement of over 13% compared to current-regulation-element-based LED drivers. Measured LED current accuracy is better than 2.8% over the entire range of the battery and its standard deviation measured across seven devices is less than 1.6%. The peak efficiencies are 90.7% and 86% at 600-and 1200-mA currents, respectively.

This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed converter achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or voltage conversion range. The D-PLL is programmable over a wide range of parameters and can be synchronized to a clock reference to ensure proper frequency lock and switching operation outside undesirable power supply resonance bands. The stability and loop dynamics of the proposed converter is analyzed using an analog equivalent PLL behavioral model which describes the dc-dc converter as a voltage-controlled oscillator (VCO). We demonstrate a 90-240 MHz single phase converter with fast hysteretic control and output conversion range of 33%-80%. The converter achieves an efficiency of 80% at 180 MHz, a load response of 40 ns for a 120 mA current step and a peak-to-peak ripple less than 25 mV. The circuit was implemented in 130 nm digital CMOS process.

This paper presents a technique to efficiently supply power over a wide power range using a fully-integrated on-chip converter for dynamic voltage scaling (DVS) based applications. All components, including filter elements, are integrated on-chip. To achieve high efficiency the converter adaptively switches between different modes of operation by detecting the output current. The design, implemented in IBM 130 nm CMOS technology, achieves a peak efficiency of 77% at reduced temperature of 8°C and has a maximum efficiency of 74.5% under normal operating conditions. The converter supplies power over a 450X output power range (0.6 mW to 266 mW). To the best of our knowledge, this is the largest reported power range for a high-efficiency, fully-integrated on-chip power converter to date.

This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 ?m CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) ?W of quiescent power, delivers up to 25 (175) ?W of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A single-inductor step-up DC-DC switching converter with bipolar outputs is implemented for active-matrix OLED mobile display panels. The positive output voltage is regulated by a boost operation with a modified comparator control (MCC), and the negative output voltage is regulated by a charge-pump operation with a proportional-integral (PI) control. The proposed adaptive current-sensing technique successfully supports the implementation of the proposed converter topology and enables the converter to work in both discontinuous-conduction mode (DCM) and continuous-conduction mode (CCM). In addition, with the MCC method, the converter can guarantee a positive output voltage that has both a fast transient response of the comparator control and a small output voltage ripple of the PWM control. A 4.1 mm2 converter IC fabricated in a 0.5 mum power BiCMOS process operates at a switching frequency of 1 MHz with a maximum efficiency of 82.3% at an output power of 330 mW.

A 0.9-V input discontinuous-conduction-mode (DCM) boost converter delivering 2.5-V and 100-mA output is presented. A novel low-voltage pulse-width modulator is proposed. The modulator can be directly powered from the 0.9-V input instead of using the 2.5-V output as in general modulator designs. Sophisticated low-voltage analog blocks, which normally consume a large amount of power and chip area, are not required in the modulator. The impact of output-voltage ripple and transient-induced output-voltage perturbation on the operation of analog blocks inside the modulator is eliminated. Boost converter start-up sequence is also greatly simplified. A CMOS-control rectifier (CCR) is also proposed to improve converter power efficiency. The CCR is used to replace the conventional rectifying switch to provide adaptive dead-time, which helps to minimize charge-sharing loss and body-diode conduction loss. Corresponding thermal stress on the rectifying switch is hence minimized. The CCR also enables the use of small off-chip inductor and capacitor at sub-MHz switching frequency to improve light-load efficiency. This converter has been implemented in a 0.35- mum CMOS process. It is designed to operate at ~ 667 kHz with a 1 mu H inductor and 4.7 mu F output capacitor to reduce both switching loss and form factor. Experimental results prove that the converter can be directly powered from 0.9-V input with ~ 85% efficiency at 100-mA output.

An integrated DC-DC hysteretic buck converter with ultrafast adaptive output transient response for reference tracking is presented. To achieve the fastest up-tracking speed, the maximum charging current control is introduced to charge up the output voltage with the maximum designed current. For down-tracking, the output is discharged by the load only to save energy. Although the converter works with hysteretic voltage mode control, an adaptive delay compensation scheme is employed to keep the switching frequency constant at 850 kHz to within plusmn2.5% across the whole operation range. The integrated buck converter was fabricated using a 0.35 mum CMOS process. With an input voltage of 3 V, the output voltage can be regulated between 0.5 and 2.5 V. With a load resistor of 10 Omega, the up-tracking speed of the maximum reference step (0.5 to 2.5 V) is 12.5 mus/V. All design features are verified by extensive measurements.

An integrated five-output single-inductor multiple-output dc-dc converter with ordered power-distributive control (OPDC) in a 0.5 mum Bi-CMOS process is presented. The converter has four main positive boost outputs programmable from +5 V to +12 V and one dependent negative output ranged from -12 V to -5 V. A maximum efficiency of 80.8% is achieved at a total output power of 450 mW, with a switching frequency of 700 kHz. The performance of the converter as a commercial product is successfully verified with a new control method and proposed circuits, including a full-waveform inductor-current sensing circuit, a variation-free frequency generator, and an in-rush-current-free soft-start method. With simplicity, flexibility, and reliability, the design enables shorter time-to-market in future extensions with more outputs and different operation requirements.

An on-chip buck converter which is implemented by stacking chips and suitable for on-chip distributed power supply systems is proposed. The operation of the converter with 3-D chip stacking is experimentally verified for the first time. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70 mA and a voltage conversion ratio of 0.7 with a switching frequency of 200 MHz and a 2 times2 mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35-mum CMOS and connected with metal bumps. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3% is also discussed.

A 1-V integrated CMOS current-mode boost converter implemented in a standard 3.3/5-V 0.6-/spl mu/m CMOS technology (V/sub TH//spl ap/0.85 V), providing power-conversion efficiency of higher than 85% at 100-mA output current, is presented in this paper. The high-performance boost converter is successfully developed due to three proposed low-voltage circuit structures, including an inductor-current sensing circuit for current-mode operation with accuracy of higher than 94%, a precision V-I converter for compensation-ramp generation in current-mode control, and a VCO providing supply-independent clock and ramp signals. Moreover, a proposed startup circuit enables proper converter startup within a sub-1-V supply condition.

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.

An integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1-/spl mu/H off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5-/spl mu/m CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters.

An oversampled A/D (analog-to-digital) converter that can be configured as either a sigma-delta converter or an incremental converter is presented. This is an oversampled instrumentation converter that cancels offset and 1/f noise. The converter architecture is based on a mixed analog-digital integrator (MADI) concept. This concept is shown to lead to a very simple and modular architecture. The implemented converter also allows selection of the converter order and the decimation factor in order to find the best tradeoff between resolution, conversion time or bandwidth, and power consumption. As the converter architecture is completely modular, it can rapidly be tailored for a specific application with minimized silicon area. The circuit achieves a resolution of 16 b on a range of +or-650 mV and compensates the offset and the even-order harmonics to a nonobservable level. >

A novel successive-approximation analog-to-digital (A/D) converter is described. It combines a string of equal-valued polysilicon resistors and a set of ratioed capacitors in a unique circuit configuration so that high sampling rate is achieved. The comparator is realized by a chopper-stabilized amplifier to reduce the effect of the offset voltages of MOS amplifiers. The converter performs an 8-b monotonic conversion with a differential nonlinearity less than 1 LSB in 0.77 mu s. The die area is 3750 mil/sup 2/. This conversion technique can also be utilized in a pipelined A/D converter and enables it to achieve high speed. >

The converter described is a feedback-type voltage regulator which supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mb dynamic RAM. It was found that an even faster access time and higher reliability compared to a conventional design could be achieved by using an on-chip voltage converter and shorter channel transistors. This voltage converter is suitable for high-density, high-speed, and high-reliability DRAMs with submicrometer transistors.