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Your search keyword '"Harshit Agarwal"' showing total 3 results
Start Over Author "Harshit Agarwal" Journal ieee journal of the electron devices society
3 results on '"Harshit Agarwal"'

1. Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

Author

Harshit Agarwal, Chetan Gupta, Pragya Kushwaha, Chandan Yadav, Juan P. Duarte, Sourabh Khandelwal, Chenming Hu, and Yogesh S. Chauhan

Subjects
BSIM6, MOSFET, SPICE, Electrical engineering. Electronics. Nuclear engineering, TK1-9971
Abstract

In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.

Published
2015
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2. Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs

Author

Harshit Agarwal, Sourabh Khandelwal, Sagnik Dey, Chenming Hu, and Yogesh Singh Chauhan

Subjects
BSIM6, Halo Doping, Flicker Noise, Compact Model, Electrical engineering. Electronics. Nuclear engineering, TK1-9971
Abstract

An improved analytical model for flicker noise (1/f noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.

Published
2015
Full Text
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3. Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs

Author

Yogesh Singh Chauhan, Harshit Agarwal, Sourabh Khandelwal, Sagnik Dey, and Chenming Hu

Subjects
Flicker Noise, Physics, Halo Doping, Semiconductor device modeling, Shot noise, BSIM6, Electronic, Optical and Magnetic Materials, Compact Model, Noise, Noise generator, CMOS, MOSFET, Electronic engineering, Node (circuits), Flicker noise, lcsh:Electrical engineering. Electronics. Nuclear engineering, Electrical and Electronic Engineering, lcsh:TK1-9971, Biotechnology
Abstract

An improved analytical model for flicker noise (1/ $f$ noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.

Published
2015

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