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In prior parts of this series, I analyzed the 1) number of all issued patents and issued computer architecture patents; 2) the prosecution time and effective patent term; 3) the number of claims, breakdown of independent and dependent claims, and effect that excess claim fees had on the numbers of total and independent claims; and 4) the type of claims (apparatus, method, or Beauregard), and effect that the Supreme Court's decision in Alice v. CLS Bank had on the number of independent and dependent method claims, for patents that were issued to 18 leading computer architecture companies and filed between 1996 and 2020. This article examines the 1) number of "backward" citations to previously issued/published U.S. patents and U.S. patent publications, foreign patents, and Other References and 2) the number of "forward" citations to a company's patent by another U.S. patent or U.S. patent publication. [ABSTRACT FROM AUTHOR]

The papers in this special section explore cutting edge research on topics that combine artificial intelligence with edge computing, relating to the design, performance, or application of microprocessors and microcomputers. [ABSTRACT FROM AUTHOR]

In their 2018 Turing Award lecture and 2019 paper, John Hennessy and David Patterson reviewed computer architecture progress since the 1960s. They projected a second golden age akin to the first, approximately 1986–1996, when new instruction set architectures, almost all reduced instruction set computers (RISCs), revolutionized the industry, eliminated most minicomputer vendors, rivaled mainframes, and began a takeover of supercomputing. The C language and derivatives came to pervade systems programming, whereas Unix derivatives came to run many servers, desktops, and smartphones. Such outcomes were not inevitable but depended on evolutionary interactions of computer architecture and languages, industry dynamics, and sometimes random coincidences. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) are growing in importance and complexity. An NN's performance (and energy efficiency) can be bound either by computation or memory resources. The processing-in-memory (PIM) paradigm, where computation is placed near or within memory arrays, is a viable solution to accelerate memory-bound NNs. However, PIM architectures vary in form, where different PIM approaches lead to different tradeoffs. Our goal is to analyze, discuss, and contrast dynamic random-access memory (DRAM)-based PIM architectures for NN performance and energy efficiency. To do so, we analyze three state-of-the-art PIM architectures: 1) UPMEM, which integrates processors and DRAM arrays into a single 2-D chip, 2) Mensa, a 3-D-stacking-based PIM architecture tailored for edge devices, and 3) SIMDRAM, which uses the analog principles of DRAM to execute bit-serial operations. Our analysis reveals that PIM greatly benefits memory-bound NNs: 1) UPMEM provides 23× the performance of a high-end graphics processing unit (GPU) when the GPU requires memory oversubscription for a general matrix–vector multiplication kernel, 2) Mensa improves energy efficiency and throughput by 3.0× and 3.1× over the baseline Edge tensor processing unit for 24 Google edge NN models, and 3) SIMDRAM outperforms a central processing unit/graphics processing unit by 16.7×/1.4× for three binary NNs. We conclude that the ideal PIM architecture for NN models depends on a model's distinct attributes, due to the inherent architectural design choices. [ABSTRACT FROM AUTHOR]

With advances in device technologies, design methodologies, and programming paradigms, microprocessors of today have undergone a complete metamorphosis compared to their predecessors from the 1970s and 1980s. In particular, heterogeneity has become an all-pervasive feature of modern-day processors in device and packaging technologies, architectures, and programming interfaces, resulting in unprecedented enhancements in their performance, power efficiency, and functionality. We explore these heterogeneous designs, from their inception in the early 2000s, to their culmination into a whole new class of processors termed as Systems-on-a-Chip, and finally track their evolution into the microprocessors of tomorrow. [ABSTRACT FROM AUTHOR]

Reports on the technology of microprocessors, focusing on the history and development of the DEC Alpha 21164. [ABSTRACT FROM AUTHOR]

It was a different computing world in the late 1980s. Many if not most researchers in the computer architecture area had become convinced that complex instruction sets such as the Intel x86 were doomed in light of the many advantages promised by reduced instruction set architecture publications. There were many voices within Intel urging upper management to abandon x86 and get started on some alternative. Even engineers who had worked on Intel's then-flagship 486 were expressing serious reservations about whether the x86 architecture could be "dragged further up the hill" to be, if not directly competitive with emerging RISC designs, at least close enough for x86 to remain profitable. [ABSTRACT FROM AUTHOR]