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The papers in this special section explore cutting edge research on topics that combine artificial intelligence with edge computing, relating to the design, performance, or application of microprocessors and microcomputers. [ABSTRACT FROM AUTHOR]

This special issue of IEEE Micro captures three contributions from among the ten regular and nine invited presentations of Cool Chips 24. The three papers are focused on convolutional neural network (CNN) acceleration, mobile deep neural network (DNN) training, and a supercomputer; were written by authors from China, Korea, and Japan, respectively; and all of them were the emerging topics at Cool Chips 24. [ABSTRACT FROM AUTHOR]

The matrix-multiply assist (MMA) facility is the latest addition to IBM's power instruction set architecture and first shipped in the recently introduced POWER10 processor. MMA is designed to accelerate matrix–matrix operations, such as matrix multiplication and convolution, using instructions that compute the outer product of vector-register operands. Outer product computations have been used for decades in linear algebra libraries to deliver high-performance implementations of matrix operations. Such libraries use conventional single-instruction–multiple-data (SIMD) instructions to emulate outer product operations. MMA in POWER10 is the first hardware with direct support for outer product operations released in the market. MMA operates with the widest diversity of data types compared to any accelerator design currently announced. Unleashing the high-performance enabled by MMA requires careful code generation. Two key considerations for optimal MMA code performance are 1) the choice of accumulation layout when maximizing the using the accumulators and 2) the selection of matrix access order. This article shows that over 92% of peak performance in POWER10 with MMA can be achieved when the code generation makes the right choices. [ABSTRACT FROM AUTHOR]