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Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

In prior parts of this series, I analyzed the 1) number of all issued patents and issued computer architecture patents; 2) the prosecution time and effective patent term; 3) the number of claims, breakdown of independent and dependent claims, and effect that excess claim fees had on the numbers of total and independent claims; and 4) the type of claims (apparatus, method, or Beauregard), and effect that the Supreme Court's decision in Alice v. CLS Bank had on the number of independent and dependent method claims, for patents that were issued to 18 leading computer architecture companies and filed between 1996 and 2020. This article examines the 1) number of "backward" citations to previously issued/published U.S. patents and U.S. patent publications, foreign patents, and Other References and 2) the number of "forward" citations to a company's patent by another U.S. patent or U.S. patent publication. [ABSTRACT FROM AUTHOR]

The papers in this special section explore cutting edge research on topics that combine artificial intelligence with edge computing, relating to the design, performance, or application of microprocessors and microcomputers. [ABSTRACT FROM AUTHOR]

Advertisement, IEEE. Subscribe and submit. For more information on paper submission, featured articles, calls for papers, and subscription links visit: www.computer.org/tbd. [ABSTRACT FROM AUTHOR]

This special issue brings to IEEE Micro's readership the best from two interesting conferences - Cool Chips 2021 and Hot Interconnects 2021. Cool Chips is a conference that focuses on the research on state-of-the-art low-power, high-speed chips and challenges facing researchers to simultaneously achieve low power consumption and high chip performance. The past couple of years have seen a flurry of research in low-power high-speed chips in artificial intelligence (AI), Internet of Things (IoT), consumer electronics, etc., and several of these were presented at the Cool Chips conference. Three selected papers from Cool Chips are presented in this issue. This special issue also presents a collection of articles on interconnect technologies based on the Hot Interconnect Conference of August 2021. Hot Interconnects is a conference that brings to light state of the art in interconnect technology. In modern systems on chip and large-scale computer systems, many processing components are being interconnected and the larger system's performance and energy consumption significantly depends on the interconnect. Five selected articles from Hot Interconnects are presented in this issue. These are briefly summarized here. [ABSTRACT FROM AUTHOR]

This special issue of IEEE Micro captures three contributions from among the ten regular and nine invited presentations of Cool Chips 24. The three papers are focused on convolutional neural network (CNN) acceleration, mobile deep neural network (DNN) training, and a supercomputer; were written by authors from China, Korea, and Japan, respectively; and all of them were the emerging topics at Cool Chips 24. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

In their 2018 Turing Award lecture and 2019 paper, John Hennessy and David Patterson reviewed computer architecture progress since the 1960s. They projected a second golden age akin to the first, approximately 1986–1996, when new instruction set architectures, almost all reduced instruction set computers (RISCs), revolutionized the industry, eliminated most minicomputer vendors, rivaled mainframes, and began a takeover of supercomputing. The C language and derivatives came to pervade systems programming, whereas Unix derivatives came to run many servers, desktops, and smartphones. Such outcomes were not inevitable but depended on evolutionary interactions of computer architecture and languages, industry dynamics, and sometimes random coincidences. [ABSTRACT FROM AUTHOR]

Advertisement, IEEE. Submit a paper today to the premier new open access journal in computing and information technology. Your research will benefit from the IEEE marketing launch and 5 million unique monthly users of the IEEE Xplore® Digital Library. Plus, this journal is fully open and compliant with funder mandates, including Plan S. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Over the last 25 years, the use of caches has advanced significantly in mainstream microprocessors to address the memory wall challenge. As we transformed microprocessors from single-core to multicore to manycore, innovations in the architecture, design, and management of on-die cache hierarchy were critical to enabling scaling in performance and efficiency. In addition, at the system level, as input/output (I/O) devices (e.g., networking) and accelerators (domain-specific) started to interact with general-purpose cores across shared memory, advancements in caching became important as a way of minimizing data movement and enabling faster communication. In this article, we cover some of the major advancements in cache research and development that have improved the performance and efficiency of microprocessor servers over the last 25 years. We will reflect upon several techniques including shared and distributed last-level caches (including data placement and coherence), cache Quality of Service (addressing interference between workloads), direct cache access (placing I/O data directly into CPU caches), and extending caching to off-die accelerators (CXL.cache). We will also outline potential future directions for cache research and development over the next 25 years. [ABSTRACT FROM AUTHOR]

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Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

Presents the introductory editorial for this issue of the publication. [ABSTRACT FROM AUTHOR]

Presents the introductory editorial for this issue of the publication. [ABSTRACT FROM AUTHOR]

Advertisement. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

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Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5× in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure $>\mathsf{10}\times$>10× higher throughput and $>\mathsf{100}\times$>100× lower latency under comparable accuracy and power envelopes. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) are growing in importance and complexity. An NN's performance (and energy efficiency) can be bound either by computation or memory resources. The processing-in-memory (PIM) paradigm, where computation is placed near or within memory arrays, is a viable solution to accelerate memory-bound NNs. However, PIM architectures vary in form, where different PIM approaches lead to different tradeoffs. Our goal is to analyze, discuss, and contrast dynamic random-access memory (DRAM)-based PIM architectures for NN performance and energy efficiency. To do so, we analyze three state-of-the-art PIM architectures: 1) UPMEM, which integrates processors and DRAM arrays into a single 2-D chip, 2) Mensa, a 3-D-stacking-based PIM architecture tailored for edge devices, and 3) SIMDRAM, which uses the analog principles of DRAM to execute bit-serial operations. Our analysis reveals that PIM greatly benefits memory-bound NNs: 1) UPMEM provides 23× the performance of a high-end graphics processing unit (GPU) when the GPU requires memory oversubscription for a general matrix–vector multiplication kernel, 2) Mensa improves energy efficiency and throughput by 3.0× and 3.1× over the baseline Edge tensor processing unit for 24 Google edge NN models, and 3) SIMDRAM outperforms a central processing unit/graphics processing unit by 16.7×/1.4× for three binary NNs. We conclude that the ideal PIM architecture for NN models depends on a model's distinct attributes, due to the inherent architectural design choices. [ABSTRACT FROM AUTHOR]

We propose hardware acceleration for a new edge computing abstraction called a Silent Witness. This abstraction embodies a severe asymmetry in the ease of write versus read operations. Surveillance data from one or more video cameras are continuously encrypted and recorded, but the decrypting, processing, or transmission of that data only occurs under stringent privacy controls. For the new search workloads of such a system, decode-enabled storage alleviates the scalability bottleneck imposed by frequent decoding of data. Our experiments show throughput improvements up to 3.5× for typical search workloads of a Silent Witness. [ABSTRACT FROM AUTHOR]

The matrix-multiply assist (MMA) facility is the latest addition to IBM's power instruction set architecture and first shipped in the recently introduced POWER10 processor. MMA is designed to accelerate matrix–matrix operations, such as matrix multiplication and convolution, using instructions that compute the outer product of vector-register operands. Outer product computations have been used for decades in linear algebra libraries to deliver high-performance implementations of matrix operations. Such libraries use conventional single-instruction–multiple-data (SIMD) instructions to emulate outer product operations. MMA in POWER10 is the first hardware with direct support for outer product operations released in the market. MMA operates with the widest diversity of data types compared to any accelerator design currently announced. Unleashing the high-performance enabled by MMA requires careful code generation. Two key considerations for optimal MMA code performance are 1) the choice of accumulation layout when maximizing the using the accumulators and 2) the selection of matrix access order. This article shows that over 92% of peak performance in POWER10 with MMA can be achieved when the code generation makes the right choices. [ABSTRACT FROM AUTHOR]

Machine learning model deployment for training and execution has been an important topic for industry and academic research in the last decade. Much of the attention has been focused on developing specific toolchains to support acceleration hardware. In this article, we present Intermediate Representation Execution Environment (IREE), a unified compiler and runtime stack with the explicit goal to scale down machine learning programs to the smallest footprints for mobile and edge devices, while maintaining the ability to scale up to larger deployment targets. IREE adopts a compiler-based approach and optimizes for heterogeneous hardware accelerators through the use of the Multi-Level IR (MLIR) compiler infrastructure, which provides the means to quickly design and implement multilevel compiler intermediate representations (IR). More specifically, this article is focused on TinyIREE, which is a set of deployment options in IREE that accommodate the limited memory and computation resources in embedded systems and bare-metal platforms, while also demonstrating IREE's intuitive workflow that generates workloads for different ISA extensions and application binary interface (ABIs) through LLVM. [ABSTRACT FROM AUTHOR]

Large cloud providers are starting to leverage liquid cooling for an increasing number of workloads. Liquid cooling enables providers to overclock server components, but they must tradeoff the potential increase in performance with higher power draw and reliability implications. We argue that two-phase immersion cooling is the most promising technology and, in that context, explore overclocking, its uses, and implications. [ABSTRACT FROM AUTHOR]

Video processing is foundational to a spectrum of important workloads: video sharing, video conferencing, photos/video archival, virtual/augmented reality, cloud gaming, and live streaming. The exponential growth in these workloads, coincident with a slowing Moore's law, poses significant challenges to deliver more computing at higher efficiencies. In this article, we present the design of a new accelerator—the video coding unit—targeted at warehouse-scale (cloud) video transcoding. Our deployment at scale in Google, the first of its kind, has demonstrated significant benefits on several products (YouTube, Meet, Stadia, Photos, etc.) serving billions of users. [ABSTRACT FROM AUTHOR]