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The matrix-multiply assist (MMA) facility is the latest addition to IBM's power instruction set architecture and first shipped in the recently introduced POWER10 processor. MMA is designed to accelerate matrix–matrix operations, such as matrix multiplication and convolution, using instructions that compute the outer product of vector-register operands. Outer product computations have been used for decades in linear algebra libraries to deliver high-performance implementations of matrix operations. Such libraries use conventional single-instruction–multiple-data (SIMD) instructions to emulate outer product operations. MMA in POWER10 is the first hardware with direct support for outer product operations released in the market. MMA operates with the widest diversity of data types compared to any accelerator design currently announced. Unleashing the high-performance enabled by MMA requires careful code generation. Two key considerations for optimal MMA code performance are 1) the choice of accumulation layout when maximizing the using the accumulators and 2) the selection of matrix access order. This article shows that over 92% of peak performance in POWER10 with MMA can be achieved when the code generation makes the right choices. [ABSTRACT FROM AUTHOR]

Vector runahead delivers extremely high memory-level parallelism even for the chains of dependent memory accesses with complex intermediate address computation, which conventional runahead techniques fundamentally cannot handle and, therefore, have ignored. It does this by rearchitecting runahead to use speculative data-level parallelism, rather than work skipping, as its primary form of extracting more memory-level parallelism in runahead mode than a true execution can, which we hope will bring about an entirely new dimension for high-performance processors. [ABSTRACT FROM AUTHOR]

It was a different computing world in the late 1980s. Many if not most researchers in the computer architecture area had become convinced that complex instruction sets such as the Intel x86 were doomed in light of the many advantages promised by reduced instruction set architecture publications. There were many voices within Intel urging upper management to abandon x86 and get started on some alternative. Even engineers who had worked on Intel's then-flagship 486 were expressing serious reservations about whether the x86 architecture could be "dragged further up the hill" to be, if not directly competitive with emerging RISC designs, at least close enough for x86 to remain profitable. [ABSTRACT FROM AUTHOR]

Much has been written of Arm's inception.1,10 Sophie Wilson and Steve Furber's original Acorn RISC Machine and the ARM1 microarchitecture in 1985. The restructuring into Advanced RISC Machines Ltd in 1990 that saw Acorn Computers, Apple, and VLSI invest together to advance this new architecture. How a small team of engineers working out of an 18th Century Turkey barn outside Cambridge, England, went on to create a business that, 30 years on, is considered a vital contributor to the global technology ecosystem. [ABSTRACT FROM AUTHOR]