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An instruction window that can tolerate latencies to DRAM memory is prohibitively complex and power hungry. To avoid having to build such large windows, runahead execution uses otherwise-idle clock cycles to achieve an average 22 percent performance improvement for processors with instruction windows of contemporary sizes. This technique incurs only a small hardware cost and does not significantly increase the processor's complexity.

For part I, see ibid., vol.13, no.4, p.8-16 (1993). Two processors that compete in the workstation/server markets are compared. The 62.5-MHz IBM RISC System/6000 Model 580 exemplifies a moderate clock rate design. The 133-1200-MHz DEC Alpha processor represents an aggressive clock rate design. The performance implications of the memory subsystems and the effect of instruction sets on path length are described. It is shown that performance measurements on many systems support the initial claim that cycle time is not sufficient to determine performance. >

The PA7100 CPU, the first precision-architecture, reduced-instruction-set-computer (PA-RISC) architecture implementation to combine an integer core and floating-point coprocessor into a single-chip format, is described. It incorporates superscalar execution and supports clock rates of up to 100 MHz in standard 0.8- mu m CMOS. Features such as a flexible primary cache organization and multiprocessing capability allow the device to be scaled to a variety of system applications, price ranges, and performance levels. The microprocessor instruction execution pipeline, cache design, translation look-aside buffer (TLB) for virtual address translation, floating-point unit, and system interface bus are discussed. The design, test, and verification methods used in the development of the PA7100 are reviewed. >

Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110's instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described. >

Important features and capabilities of the 80960 are briefly examined, and an overview of its architecture is given. A detached discussion is presented of the register model, core instruction set, register operations, memory operations, control operations instruction cache, user-supervisor protection, interrupts, faults, and debug support. >