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This Letter describes a current-reuse class-B/C hybrid voltage-controlled oscillator (VCO) with robust startup, enhanced phase noise and differential balancing at small area and power. Specifically, an asymmetrical CMOS class-C core is aided by a symmetrical NMOS-only class-B core that effectively shares the bias current for deeper class-C operation of the former; wider margin of startup against PVT variations, and lower amplitude imbalance against oscillation frequencies. Moreover, this topology adds the freedom of adjustable peak dynamic current and boosts the oscillation swing at low power. The spiral inductors with patterned ground shields shrink the die size. Fabricated in 65 nm CMOS, the 0.07 mm^2 VCO prototype exhibits 10.15-to-11.17 GHz tunability, and -107.73-dBc/Hz phase noise at 1 MHz offset, while dissipating merely 2.2 mW at 1.2 V. The achieved area-included figure-of-merit (FoMA = 196 dBc/Hz) favorably compares with the state-of-the-art. [ABSTRACT FROM PUBLISHER]

A compact realization of hybrid class-B/C quadrature voltage-controlled oscillator (QVCO) with output buffering is proposed. It employs a four-phase amplitude detector feedback loop to shift the operation mode from hybrid class-B/class-C to class-C after power up. The power-efficient class-C core allows quadrature-locking via passive capacitive coupling, whereas the auxiliary class-B core ensures a robust startup. For higher output drivability, PMOS-based source followers are stacked atop the QVCO for reusing its bias current and avoiding any AC-coupling networks. The buffered QVCO can directly drive up the 50-\Omega port of testers, or to withstand a large capacitive load in on-chip signal distribution. The fabricated 9 GHz QVCO in 65 nm CMOS draws 10.5 mW and exhibits -99.37-dBc/Hz phase noise at 1 MHz offset. The active area is just 0.137 mm^2 by using two compact spiral inductors with patterned ground shields. [ABSTRACT FROM PUBLISHER]