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This letter describes the analysis, design, and measured results of a fully integrated single-pole double-throw (SPDT) switch developed in 0.25- \mu \textm silicon– germanium (SiGe) BiCMOS process technology, which features SiGe HBTs with peak fT/f{{\text {max}}} of 110/180 GHz. The switch is designed based on a shunt–shunt topology with a combination of various design and layout optimization approaches to improve the insertion loss (IL), isolation, and power handling capability. The designed switch including the applied techniques results in a measured IL of 2.3 dB and isolation of 32 dB at 8 GHz. The switch is able to attain a state-of-the-art input referred 1-dB compression point (IP1 dB) up to 30 dBm while drawing a current of 3 mA from a 6 V supply. The die has an area of only 775\,\,\mu \text m\,\,\times 820\,\,\mu \textm . To the author’s knowledge, the presented work is the first SPDT switch ever reported, that incorporates slow-wave transmission lines and reverse-saturated heterojunction bipolar transistors at the specified frequency range. [ABSTRACT FROM PUBLISHER]

This letter presents a 7-bit CMOS step attenuator for the first time in the literature, designed with isolated NMOS (iNMOS) using IHP 0.25 \mu\textm SiGe BiCMOS process technology. INMOS' are utilized to decreasethe insertion loss (IL) caused by internal parasitic capacitances, which is especially important when cascading 7 attenuation stages. The attenuator has a measured maximum relative attenuation of 16.51 dB with an increment of 0.13 dB while exhibiting a root mean square (RMS) amplitude error of less than 0.13 dB, the lowest error ever reported. In addition, the attenuator exhibits an RMS phase error of 2.7° at 10 GHz. The measured input referred 1 dB compression point (\textIP1\;\mathrm{dB}) of the attenuator is 12.5 dBm at 10 GHz. Moreover, the attenuator demonstrates an IL of less than 12.5 dB in X-band (8–12 GHz). The total chip area excluding pads is 0.29 mm2. [ABSTRACT FROM PUBLISHER]