Search

This letter presents a $D$ -band low-noise amplifier (LNA) in 250-nm InP HBT technology for the next-generation wireless applications. The LNA has a measured peak gain of 13 dB, a 3-dB bandwidth greater than 20 GHz (120–140 GHz), and a measured noise figure (NF) of less than 6 dB in the band. A reduction in the 3-dB bandwidth from simulation was observed during the measurements which was attributed to the substrate waves using full chip electromagnetic (EM) simulation. EM simulations show that a partial or complete removal of the back side metallization of the InP substrate, holes in metal-1 ground plane, or a strategic placement of through-substrate vias suppress these substrate waves. To the authors’ knowledge, this is the first 120–140-GHz LNA in the InP 250-nm HBT technology. [ABSTRACT FROM AUTHOR]

This letter presents a wideband high-speed static 1/2 frequency divider using a 0.8- ${\mu }\text{m}$ indium phosphide (InP) process. In this design, some performance-enhanced unity-gain frequency (${f_{T}}$) doubler structures are proposed and compared. Moreover, the application of an enhanced ${f_{T}}$ -doubler technique, for the first time, improves the radio-frequency (RF) performance of the emitter-coupled logic (ECL) divider. The divider has better than 0.4– ${f_{T}}$ frequency ranges from 0.2 to >66 GHz (single-ended sine wave input) within 165-GHz transistor ${f_{T}}$. The input-referred self-oscillation frequency (SOF) of the divider is 53.9 GHz, and the single-ended signal output power is from −5 to 2 dBm. The measured results confirm a great improvement in the performance of the ECL divider by using the enhanced ${f_{T}}$ -doubler structure. [ABSTRACT FROM AUTHOR]

This letter presents a nanowatt-level detector-first wakeup receiver using microelectromechanical system (MEMS)-based matching network (MN). The aluminum nitride (AlN) piezoelectric MEMS resonator is utilized to implement the impedance MN for high passive gain to improve the receiver sensitivity. The high- $Q$ MEMS-based MN also greatly improves the receiver’s out-of-band interference rejection. Gate-biased envelope detector (ED) with small input capacitance is used for RF-to-baseband direct conversion. The wakeup receiver is implemented in a 180-nm CMOS process. It obtains −57-dBm sensitivity with 1-kbps ON-OFF keying (OOK) data rate at 789 MHz while consuming only 16-nW power consumption. [ABSTRACT FROM AUTHOR]

In this work, we present a new class of thickness extensional microelectromechanical resonator, the overmoded bulk acoustic resonator (OBAR) for filtering applications in the 5G millimeter wave (mm-wave) spectrum. This resonator operates in a second overtone thickness mode with approximately equal thickness electrodes and piezoelectric layer so that acoustic energy is distributed evenly between the different layers. Compared to a fundamental mode at a fixed frequency, the OBAR possess a $3\times $ thicker piezo layer and 5– $10\times $ thicker metal electrodes, enabling manufacturable 30–60 GHz devices. We demonstrate the OBAR experimentally through fabrication of a Pt-AlN-Al device with electromechanical-coupling coefficient ($k_{t}^{2}$) of 1.7%, and series resonance quality factor ($Q_{s}$) of 110 at 33 GHz. [ABSTRACT FROM AUTHOR]

This letter reports on a 108-GHz bandwidth 0.5- $\mu \text{m}$ InP DHBT analog-multiplexer-driver (AMUX-driver). To the best of the authors’ knowledge, this 2:1 AMUX-driver shows unprecedented 1.9-Vppd 160-GSa/s 160-GBd non-return-to-zero (NRZ) and 2.4-Vppd 100-GSa/s 100-GBd PAM-4 output swings, with very high-quality eye diagrams, without any digital signal processing (DSP) or postprocessing. Up to 3.2 Vppd is obtained in NRZ at 100 GBd. The lumped AMUX-driver also shows record 25.7-dB gain and 2.08-THz gain-bandwidth product with 11.1-dB equalizing capabilities at 86.6 GHz. [ABSTRACT FROM AUTHOR]

We report a five-gain-stage 150–175-GHz solid-state power amplifier (PA, SSPA) monolithic microwave integrated circuit (MMIC) having modest 20–21-dBm output power $P_{\mathrm {out}}$ , high gain, and high power-added efficiency (PAE). The transistor technology is 250-nm InP HBT. The $S_{21}$ gain is 31.4 ± 1.2 dB from 100 to 178 GHz. The 3-dB $S_{21}$ bandwidth is between 96 and 181 GHz. Typical return loss values for $\vert S_{11}\vert $ and $\vert S_{22}\vert $ exceed 8.5 and 10 dB, respectively. The dc power is 0.72 W. Across 150–175 GHz, the saturated output power $P_{\mathrm {sat}}$ is 106–126 mW with 16–18-dB gain and 12.5%–16.2% PAE—peak values for $P_{\mathrm {out}}$ , gain, and PAE are at 170-GHz operation. The 1-dB gain compression $P_{\mathrm {out}}$ (OP $_{\mathrm {1\,dB}}$) is 30–60 mW. Across the $D$ -band (110–170 GHz), $P_{\mathrm {sat}}$ is 82–126 mW with 9.1%–16.2% PAE. This work establishes a 1.62– $1.89\times $ increase to PAE over 150–175 GHz operation at the output power and gain levels cited. It is also the highest RF output power demonstrated across the full 110–170-GHz WR6.5 waveguide band. [ABSTRACT FROM AUTHOR]

This letter presents a 67–116-GHz low-noise amplifier (LNA) module with state-of-the-art cryogenic noise performance. The LNA is based on a monolithic microwave integrated circuit (MMIC) that is fabricated in a 50-nm metamorphic high-electron-mobility transistor (mHEMT) technology. The MMIC is packaged in a WR10 waveguide split-block housing and uses fused silica ${E}$ -plane microstrip-to-waveguide transitions. For a 67–116-GHz bandwidth, the amplifier exhibits average noise temperatures (${T}~_{{\text {e}}}$) at 15 and 300 K of 21.4 and 194 K, respectively. A minimum ${T}~_{{\text {e}}}$ of 13.6 K is achieved at 72.2 GHz. To the best of the authors’ knowledge, this LNA demonstrates a new low-noise benchmark for room temperature and cryogenic noise temperatures in the extended ${W}$ -band frequency range. [ABSTRACT FROM AUTHOR]

In this letter, we present a 25-GSa/s wideband track-and-hold amplifier using 0.8- ${\mu }\text{m}$ indium phosphide (InP) process for high-speed analog sampling front-end. In this design, an active peaking input buffer is first used in the base–collector switching diode sampler. Moreover, it is carefully calculated and analyzed. The dominant pole in the signal path of the circuit is canceled by one zero produced by the active peaking structure; therefore, the bandwidth (BW) is extended. The experimental results show that a total harmonic distortion (THD) of less than −27 dBc and a spurious-free dynamic range (SFDR) of better than 32.5 dB are demonstrated at a 25-GSa/s sampling rate. In the hold mode, the isolation is better than −42 dB. In addition, it has an 0.156 ${f_{T}}$ BW from dc to 25 GHz within 160-GHz ${f_{T}}$ , which is a very competitive value compared with other reported track-and-hold amplifiers (THAs) using the InP process. [ABSTRACT FROM AUTHOR]

This letter presents a WR-1.5 frequency doubler implemented in a 130-nm InP heterojunction-bipolar-transistor (HBT) technology. The doubler core uses a differential common-emitter transistor to improve the stability and to ease the fundamental suppression. The output power is maximized by the source-pull and load-pull simulation. The input and output matching to the optimum impedance is implemented using a single transmission line. This simple matching structure reduces the modeling inaccuracy and the passive component loss at the terahertz frequencies. The output power of the doubler was measured in the frequency range of 590–610 GHz. The doubler exhibits the maximum output power of −5 dBm and conversion loss of 14 dB at 590 GHz without additional drive amplifiers. [ABSTRACT FROM AUTHOR]

Performances of high-speed switches operating as terahertz on–off-keying (OOK) modulators are reported. Two types of switches, a passive shunt switch and an amplifier switch, are fabricated using 0.25- $\mu \text{m}$ InP double heterojuction bipolar transistor (DHBT) technology. Small-signal tests show that the amplifier switch possesses superior on–off ratio, but the passive switch has broader bandwidth and smaller group delay ripples. A modulator test setup is built with 20-dB path loss between the transmitter and the receiver. The results indicate that carrier power levels of 14 dBm for the shunt switch and 8 dBm for the amplifier switch are required for 20-Gb/s OOK modulation with bit error rate (BER) of 10−2 at 290 GHz. [ABSTRACT FROM AUTHOR]

We report here a compact 140-GHz, 150-mW high-gain solid-state power amplifier (SSPA) monolithic microwave integrated circuit (MMIC) demonstrated in a 250-nm InP HBT technology. It utilizes five-gain stages and two-way on-chip power combining. The amplifier measures 29.5-dB mid-band $S_{21}$ gain and over 125-mW output power across 115–150-GHz operation. The peak 153-mW output power was measured at 140 GHz using only 2.7-mW RF input power—the associated large-signal gain is 17.5 dB with 9.8% power added efficiency (PAE). The 140-GHz OP1 dB 1-dB gain compression power is 106 mW with 7.0% PAE. The dc power dissipation is 1.54 W and its size is only 0.75 mm2. The 3-dB $S_{21}$ gain roll-off is between 112 and 147 GHz. The 115–150-GHz output power variation at 0-dBm input drive is only ±0.5 dB. The peak PAE varies between 8.2% and 10.5%. This D-band result improves upon by $2.3\times $ at 140 GHz the state-of-the-art peak RF power previously demonstrated by SSPA MMICs. [ABSTRACT FROM AUTHOR]

In this letter, we present a research on the application possibility of the integrated planar spatial (IPS) combiner in terahertz monolithic integrated circuits (TMICs). The IPS combiner has several attractive characters, such as low loss and good port-to-port isolation. Measured insertion loss of the back-to-back four-way IPS combiner prototype is less than 1.65 dB from 220 to 260 GHz. Then, the IPS power combiner is applied to a four-way six-stage common-emitter InP double heterojunction bipolar transistor amplifier based on a 0.5- $\mu \text{m}$ process. With the help of the IPS combiner and the compact circuit design, this letter greatly improves the output power and output power density compared with other TMICs of the same InP HBT technology. The output power density per unit emitter length (output stage) is 0.51 mW/ $\mu $ m, which is at the same level of amplifiers based on the 0.25- $\mu \text{m}$ InP HBT technology. [ABSTRACT FROM AUTHOR]

This letter presents a 1 to >110-GHz ultrawideband traveling-wave amplifier (TWA) based on 500-nm transferred-substrate InP double-heterojunction bipolar transistor technology. The HBT cells are realized with inductive peaking at the output and match the phase delay between individual stages. The collector bias is slightly below the value for the maximum current gain. This allows a frequency-invariant high-output power characteristic with a flat group delay. The amplifier exhibits a gain of 13 dB with a measured bandwidth of 1–110 GHz and a uniform 10-dBm 1-dB compression output power with an associated maximum PAE of 8% at 110 GHz. To the best of our knowledge, this is the highest PAE and the maximum flat output power reported for such a TWA covering frequencies up to 170 GHz. The amplifier consumes only 129 mW, which is among the lowest dc power dissipations reported for the given gain–bandwidth product. Moreover, the group delay is flat across the band, which makes the TWA very useful in high-speed optical communication systems. [ABSTRACT FROM AUTHOR]

This letter presents a novel advancement in acoustic-wave-lumped-element-resonator (AWLR) filters, which improves transmission zero isolation by over 40 dB without adding any additional components. By spacing and orienting the AWLR-lumped inductors for intentional magnetic coupling, a hybrid bandpass-absorptive-bandstop filter is generated. The filter is demonstrated in three configurations using aluminum nitride contour-mode resonators and off-the-shelf lumped elements. Measured performance of as low as 3.2-dB insertion loss, bandwidth of 0.87%, and transmission zero notch depth greater than 60 dB is shown. [ABSTRACT FROM AUTHOR]

A single-chip active frequency tripler circuit with output at F-band (90–140 GHz) is presented. A common-emitter transistor stage with input and output matching circuits is used to produce the third harmonic, followed by a five-pole band-pass filter and a wideband four-stage power amplifier to amplify and increase the output power. The circuit is implemented in a 250-nm InP double-heterostructure bipolar transistor technology with ft/fmax 350/650 GHz, respectively. The chip achieves a peak output power of 14.2 dBm from 99 to 126 GHz at 2-dBm input power and conversion gain of 13 dB at −2-dBm input power. The measured 3-dB output bandwidth is 51 GHz from 90 to 141 GHz which corresponds to 44.2% relative bandwidth. It demonstrates up to 23-dBc rejection ratio of the first and the second harmonics. The dc power consumption is 156 mW at 2-dBm input power. The chip size is 0.9 \times 0.96\,\,\text mm^2 including pads and achieves a power efficiency of 16.7%. [ABSTRACT FROM PUBLISHER]

This letter reports on two power amplifier (PA) monolithic microwave-integrated circuits operating at W-band. The PAs use 250 nm InP HBTs and thin-film microstrip topology formed with benzocyclobutene dielectric. First PA utilizes a two-emitter finger HBT unit cell with each finger having emitter area of 0.25 \times 6~\mu \textm^2 . Second PA power combines two HBT unit cells. Both amplifiers are single stage and utilize conjugate matching at the input and optimum power load matching at the output. The first amplifier has demonstrated saturated output power of 12.4 dBm and power-added efficiency (PAE) of 41.7% at 93 GHz. This is the highest PAE number demonstrated at W-band. Second amplifier has demonstrated saturated output power of 15.6 dBm and PAE of 21.1% at 89 GHz. [ABSTRACT FROM PUBLISHER]

We report a heterogeneously integrated W-band downconverter, consisting of a low noise amplifier (LNA) and a star mixer. An LNA is realized in a 0.1- \mu \textm InP high-electron-mobility transistor (HEMT) technology and features the noise figure of ~2.5 dB and gain ≥25 dB at W-band. Star mixer is realized in four-layer interconnect InP heterojunction bipolar transistor (HBT) and diode process. A novel design eliminates electrically large diode ring by utilizing a multimetal configuration. Mixer chiplet is integrated into the LNA carrier wafer using heterogeneous integration, which offers electrically short connection between two technologies. Heterogeneously integrated interconnect or transition has measured a loss of ~0.8 dB up to 96 GHz. Integrated W-band downconverter has measured the conversion gain ≥0 dB from 87 to 100 GHz. This is a first reported integration of InP HBT chiplets into the InP HEMT wafer using heterogeneous integration, as well as first reported a W-band heterogeneously integrated downconverter. [ABSTRACT FROM PUBLISHER]

A 280-GHz high-power signal source has been developed in this work based on a 250-nm InP heterojunction bipolar transistor (HBT) technology. The fabricated signal source is composed of two in-phase locked common-base cross-coupled oscillators, the output of which is on-chip combined by a pair of rat-race couplers and a Wilkinson power combiner for enhanced output power. The developed signal source exhibits an oscillation frequency of 276.4 GHz and a phase noise of–89 dBc/Hz at 1 MHz offset. The output power of the signal source is measured to be 10 dBm (10 mW), while consuming a dc power of 196 mW (dc-to-RF efficiency of 5.1%). [ABSTRACT FROM PUBLISHER]

In this work we demonstrate high values of electromechanical coupling coefficient ( kt^{2} ) exceeding 4.9% in 1- \mu \text m thick Aluminum Nitride (AlN) two-dimensional-mode resonators (2DMRs) operating around 3.2 GHz. Such a high kt^{2} -value, which is attained thanks to the transduction of the resonators through both the d33 and d31 piezoelectric coefficients of AlN, enables low-power oscillators and low insertion-loss filters, operating in the Super-High-Frequency (SHF) range. [ABSTRACT FROM PUBLISHER]

In this letter, a packaged Low Noise Amplifier (LNA) operating at 670 GHz is presented. The LNA uses a new generation of 25 nm InP HEMT with 1.5 THz \text f\mathrm {MAX} . The eight-stage amplifier shows approximately 16 dB associated gain in package with a noise figure ranging from 9.4-9.9 dB measured across a 15 GHz bandwidth. These results represent better than 3 dB improvement in sensitivity to previously published InP HEMT results, and represent the lowest measured noise figure for any LNA at this operating frequency. [ABSTRACT FROM PUBLISHER]

This letter presents a G-band balanced frequency doubler with high output power, realized using a 800 nm transferred-substrate InP-HBT process. The doubler delivers 5\ dBm \pm 3 dBm in the range 140–220 GHz. The dc consumption is only 41 mW. To the knowledge of the authors, this is the highest output power for a wideband transistor based frequency doubler in the 140–220 GHz frequency range published so far. The results show the ability to implement a high output power G-band source in transferred-substrate InP HBT technology. [ABSTRACT FROM PUBLISHER]

In this letter, we demonstrate the first 400 GHz multiplier chain with integrated buffer amplifiers through the chain. The x9 multiplier chain uses 25 nm InP HEMT MMIC technology. The chain consists of three packaged MMICs in split-block waveguide packages with each multiplier incorporating an integrated output buffer. We report a peak output of 6.9 mW and greater than 4 mW over a 10% bandwidth. [ABSTRACT FROM PUBLISHER]

A 290–307.5 GHz solid-state power-amplifier MMIC is presented demonstrating 6–10 mW Pout for Pin < 0.8 mW. PDC is 848 mW. This represents 10–12 dB of large-signal gain across 18 GHz of high-power bandwidth. This 3-stage amplifier has peak 23.5 dB S21 gain at 299 GHz, a 1 dB bandwidth from 292–303 GHz, and a 3 dB bandwidth from 285–306 GHz. A power-cascode cell topology is used for the PA unit cell and 2:1 Wilkinson power combining of these cells (32 um HBT output periphery) achieves the RF powers claimed. The insertion loss demonstrated by the combiner is 0.45–0.5 dB from 255–330 GHz—this improves upon state-of-the-art for on-wafer 2:1 combining at these frequencies by 0.3–0.7 dB. This work represents the first demonstration of a 300 GHz power cascode cell topology with output power and output power density (W/mm) competitive with state-of-the-art PAs with 10 mW Pout. [ABSTRACT FROM PUBLISHER]

This letter reports about unpatterned ferromagnetic NiFe/AlN multilayer composites used as advanced magnetic core materials for on-chip and interposer integrated inductances. The proposed composite structure reduces RF induced currents and thus pushes the permeability cutoff to beyond 3.7 GHz, which is by a factor of 7.1 higher than for homogeneous NiFe layers of same thickness. To the best knowledge of the authors, we achieve the highest effective relative permeability of 28 at 1 GHz, highest ferromagnetic resonance frequency and highest inductance enhancement factor above 1 GHz ever reported for devices based on on-chip unpatterned NiFe magnetic cores. A single loop inductor is also implemented as a technology demonstrator, achieving an inductance enhancement of 4.8 and a quality factor enhancement of 4.5 at 400 MHz. [ABSTRACT FROM PUBLISHER]