Search

This study presents a compact rectifier array with an adaptive power distribution network (APDN). The rectifier array comprises rectifier cell 1 for both high-power mode and high-frequency band; rectifier cell 2 for both low-power mode and low-frequency band; and a power distribution network, which adaptively distributes power according to the input power and frequency. The proposed APDN is merged with input matching networks of the subrectifiers to achieve low insertion loss and high compactness with wideband characteristics. For validation, the proposed rectifier array was designed, implemented, and measured. The measurement results show that the power conversion efficiency (PCE) is over 50% within an input power range of 9.9–30.8 dBm. A peak PCE of over 50% is realized at a frequency range of 0.1–2.7 GHz.

A W-band differential frequency doubler using a current-reuse configuration in a 65 nm CMOS process is presented in this letter. The differential current-reuse circuit with a second harmonic coupling transformer is introduced to improve conversion gain at small input powers minimizing the effect of the RF bypass capacitor. The proposed circuit achieves a conversion gain of $0.8\sim -4.2~{\rm dB}$ and a fundamental rejection above 19 dB in the input frequency range of 36.5~44 GHz with $-4 ~{\rm dBm}$ input power. It has conversion gain variation below 1 dB when the input power varies from $-7.4$ to 0.1 dBm at 77 GHz. The dc power consumption is 14 mW. It has the highest conversion gain with the smallest chip size of 0.22 ${\rm mm}^{2}$ among all V-/W-band CMOS frequency doublers.