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Cluster tools play a significant role in the entire process of wafer fabrication. As the width of circuits in semiconductor chips shrinks down to less than 10nm, strict operational constraints are imposed on the operations of cluster tools in order to ensure the quality of processed wafers. Particularly, wafer residency time constraints and chamber cleaning requirements are commonly seen in etching, chemical vapor deposition, coating processes, etc. They make the scheduling problem of cluster tools more challenging. This work aims to provide a solution for dual-arm cluster tools with wafer residency time constraints and chamber cleaning requirements. To do so, it proposes a novel virtual wafer-based scheduling method. By this method, under a steady state, a PM processes either a real or virtual wafer at a time. When a PM processes a virtual one, its chamber can perform a cleaning operation. In this way, we can meet not only the strict residency time constraints for real wafers, but also innovatively meet chamber cleaning requirements. Based on such a novel scheduling method, an efficient binary integer programming model is established to optimize the throughput of cluster tools. Finally, experiments are performed to show the efficiency and effectiveness of the proposed method. Note to Practitioners—To ensure wafer quality in semiconductor manufacturing, engineers have to impose wafer residency time constraints and chamber cleaning requirements on the operations of cluster tools. In order to tackle their scheduling problem with these constraints, this work proposes a novel method based on the use of virtual wafers. Under a one-cyclic schedule obtained for time-constrained cluster tools without chamber cleaning requirements, virtual wafers are loaded into the tool such that when a PM processes a virtual wafer, a chamber cleaning operation can be performed in practice. The key to solve this scheduling problem is to find a wafer loading sequence with the highest performance in terms of cycle time. To do so, this work establishes an efficient binary integer programming model to search for such a solution. Since the obtained solution is a periodical wafer loading sequence based on a one-wafer cyclic schedule, it can be easily implemented. Therefore, this work has a high practical value to numerous semiconductor manufacturers. [ABSTRACT FROM AUTHOR]

Deadlocks are a highly undesirable situation in flexible manufacturing systems (FMSs). This article presents a direct and novel method to detect such markings by constructing the resource flow graph of a Petri net that models an FMS and to recover such markings by adding a set of recovery transitions. First, an algorithm is developed to build a new kind of directed graph called the resource flow graph of a Petri net. Resource flow graphs can well represent the competition for shared resources by different processes. Second, based on the resource flow graph, loop graphs can be found. Furthermore, partial deadlock markings can be easily detected due to their relationship with loop graphs. Then, we propose an algorithm to design a set of recovery transitions for loop graphs that are enabled at partial deadlock markings. The proposed approach can detect partial deadlock markings without generating a complete reachability graph of a Petri net and the resulting net is deadlock-free with all reachable markings by adding the obtained recovery transitions. Finally, some widely used examples are provided to demonstrate the proposed approach. Note to Practitioners—The occurrence of deadlocks in an FMS tends to cause unnecessary productivity costs and even catastrophic results. In the framework of Petri nets, reachability graph analysis can usually obtain a maximally permissive supervisor of a plant. However, it is rather inefficient since it suffers from the state explosion problem. In this particular research, we develop an off-line deadlock detection and recovery policy by setting a group of virtual events that are not present in a physical model. The proposed approach is computationally efficient since it does not require to generate a reachability graph. It guarantees that the resulted system is deadlock-free with its all original reachable markings. [ABSTRACT FROM AUTHOR]

Nowadays, wafer fabrication in semiconductor manufacturing is highly dependent on cluster tools. A cluster tool is equipped with several process modules (PMs) and a wafer handling robot. When the tool is operating, generally each PM is processing a wafer, and the robot is responsible for delivering the wafers from one PM to another. Thus, when a wafer is completed in a PM, the robot may be busy for performing other tasks such that it cannot immediately unload the completed wafer in the PM, resulting in that the wafer has to stay there for some extra time. The processing time of a wafer together with its delay time for waiting for the robot’s arrival for unloading is defined as wafer residency time in a PM. However, a long wafer delay time may deteriorate its quality. Therefore, it is highly desired and important to reduce the wafer delay time at each step as much as possible. This work aims to tackle this important issue for single-arm cluster tools (SACTs). Specifically, by using a Petri net model, this work analyzes the steady-state operational behavior of an SACT under the backward and earliest starting strategies. It is found that there must exist wafer delay time at the steps in the upstream of the bottleneck step, and such wafer delay time can be reduced by properly adjusting the robot waiting time. Thus, three algorithms are developed to reduce the wafer delay time at each step as much as possible by properly assigning the robot idle time. Finally, the application of the proposed method is illustrated by using examples. Note to Practitioners—In a modern semiconductor fab, there are hundreds of cluster tools for wafer fabrication. To ensure wafer quality, it is important to reduce the wafer delay time in PMs of cluster tools after a wafer is processed since the high temperature, chemical gas, and particles in the PMs may damage the wafer. To do so, this work proposes three algorithms with polynomial complexity to assign the robot idle time as robot waiting time such that the wafer delay time in PMs can be reduced as much as possible. Furthermore, the obtained schedule by these algorithms is optimal in terms of the cycle time. Besides, the developed algorithms can be easily embedded into the controller of cluster tools by facility engineers. Therefore, this work has a practical value. [ABSTRACT FROM AUTHOR]

A fundamental requirement of the supervisory control theory (SCT) of discrete-event systems is a finite automaton model of the plant. The requirement does not hold for black-box systems whose source code and logical model are not accessible. To apply SCT to black-box systems, we integrate automaton learning technology with SCT and apply the new method to improve the requirements conformance of software reuse. If the reused software component does not satisfy a requirement, the method adds a supervisor component to prevent the black-box system from reaching “faulty sections.” The method employs learning-based testing (LBT) to verify whether the reused software meets all requirements in the new context. LBT generates a large number of test cases and iteratively constructs an automaton model of the system under test. If the system fails the test, the learned model is applied as the plant model for control synthesis using SCT. Then, the supervisor is implemented as an executable program to monitor and control the system to follow the requirement. Finally, the integrated system, including the supervisory program and the reused component, is tested by LBT to assure the satisfiability of the requirement. This paper makes two contributions. First, we innovatively integrate LBT and SCT for the control synthesis of black-box reactive systems. Second, software component reuse is still possible even if it does not satisfy user requirements at the outset.

Note to Practitioners—In black-box software reuse, if a component does not satisfy user requirements in a new context, the developer has to abandon it and develop a new one, which is costly. The proposed method enables software reuse for black-box reactive systems by combining learning-based testing (LBT) and supervisory control theory (SCT). LBT can test whether the requirements hold in new settings and infer hypothesis models of the component at the same time. If the component does not pass the test, the learned hypothesis is used as a plant model to compute a supervisor using SCT. Then, a supervisory program is developed according to the control actions of the supervisor to govern the system to follow the behavior of the requirements. We illustrate the proposed method through an example of a simple cruise control module. The effectiveness of the new method is demonstrated with a larger software component brake-by-wire with floating point data types. The case studies show not only the methodology of the new approach but also a working tool chain to perform it. [ABSTRACT FROM PUBLISHER]

The recent developments of technologies in Internet of Things (IoT) provide the opportunities for smart manufacturing with real-time traceability, visibility, and interoperability in production planning, execution, and control. To fulfill this target, this work presents a real-time production performance analysis and exception diagnosis model (PAEDM). By this model, hierarchical-timed-colored Petri net (HTCPN) with smart tokens that change just like smart objects in practice is used to analyze the sensor data such that the critical performance information can be perceived. Decision Tree is used to diagnose exceptions from the critical production performance, so that persuasive qualitative and quantitative exception information can be extracted accurately. The presented method is demonstrated by a case study and simulation results show that PAEDM can be used to effectively analyze production performance and exceptions in real-time for dynamic and stochastic manufacturing processes. [ABSTRACT FROM PUBLISHER]

With wafer residency time constraint of cluster tools in semiconductor manufacturing, activity time variation can make an originally feasible schedule infeasible. Thus, it is difficult to schedule them and schedulability is a vitally important issue. With bounded activity time variation considered, this paper addresses their real-time scheduling issues and conducts their schedulability analysis. A Petri net (PN) model and a control policy are presented. Based on them, this paper derives closed-form schedulability conditions. If schedulable, an algorithm is developed to obtain an offline periodic schedule. This schedule together with the control policy forms a real-time schedule. It is optimal in terms of cycle time and can be analytically computed, which represents significant advance in this area. [ABSTRACT FROM PUBLISHER]

For short-term scheduling of crude oil operations in refinery, often crude oil residency time constraint and charging-tank-switch-overlap constraint are ignored by mathematical programming models to make the problem solvable. Thus, a schedule obtained by such mathematical programming models is infeasible and cannot be deployed. To solve this problem, this work studies the short-term scheduling problem of crude oil operations in a control theory perspective. The system is modeled by a hybrid Petri net and a short-term schedule is seen as a series of control commands. With this model, schedulability analysis is carried out and schedulability conditions are presented. These conditions can be used as constraints for finding a realizable and optimal refining schedule. Moreover, based on the proposed approach, a detailed schedule can be easily obtained given a realizable refining schedule. In this way, the complexity for the short-term scheduling problem of crude oil operations in refinery is greatly reduced and effective techniques and tools for practical applications can be obtained. [ABSTRACT FROM AUTHOR]

For some wafer fabrication processes in cluster tools, e.g., atomic layer deposition (ALD), wafer revisiting is required. Typically, in such processes, wafers need to visit two consecutive processing steps several times. Such a revisiting process can be denoted as (mi, mi + 1)^h, where i means the ith-step and mi and mi + 1 mean the corresponding quantity of the processing modules in i and (i+1)th steps, and h the number of visiting times. This paper conducts a study for scheduling single-arm cluster tools with such a wafer revisiting process. The system is modeled by Petri nets (PNs) to guarantee the feasibility of robot activities. Based on the model, a deadlock avoidance policy is presented. With the control policy, cycle time analysis for the revisiting process is made. With the fact that wafer processing times are much longer than robot movement times in cluster tools, it is shown that, when mi = mi + 1 = 1, i.e., each step has only one processing module, the optimal one-wafer cyclic schedule is deterministic and unique, and the minimal cycle time can be calculated by an analytical expression. It is also shown that, when mi = 1 and mi + 1 = 2 or mi= 2 and mi + 1 = 1, the optimal one-wafer cyclic schedule can be obtained by finding h deterministic schedules and the one with the least cycle time. A novel analytical method is finally presented to schedule the overall system containing such reentrant wafer flow. This represents a significant advance in single-arm cluster equipment automation. [ABSTRACT FROM AUTHOR]