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A generalized algorithm for forming interconnections between points on a multilayer circuit board is described and evaluated. The algorithm treats interconnections on individual layers and connections between layers by means of plated holes. Generalizing the well-known Lee algorithm and using its terminology, this algorithm makes use of a coded C array that is stored in memory and records the state of the multilayer circuit board. Completed paths, possible remaining paths between points to be connected, and circuitboard interconnection restrictions are recorded in the coded C array. The algorithm consists of five iterative steps that involve decisions on the basis of the state of the circuit board as stored in the C array. All possible routes are attempted, and the routing sequence is stopped when the path is completed or all attempted path routes are exhausted. A number of modifications to the algorithm permitting various circuit connection constraints to be satisfied are also presented. The algorithm has been programmed for a GE-635 computer. Typical results for some of the printed circuit boards that were used to evaluate the algorithm are included.

Both ac and dc automated network design algorithms have been shown to be feasible and practical in the design of lumped linear networks. The present paper extends and combines these algorithms to integrated circuit amplifiers, where the ability to "grow" transistors to attain specified design goals is mandatory. In particular, it is shown that under the reasonable assumption that certain fabrication parameters are held fixed, suitable design parameters for transistors are the area and the perimeter of the emitter and the dc collector current. Transistor models can be derived in terms of these parameters. The rather general ac-dc design algorithm described allows transistors to grow to meet ac specifications; dc design requirements arise naturally. Two examples are used to show the tractability of the approach: 1 ) a differential pair of transistors is designed for given ac and dc specifications; 2) a cascade amplifier is designed for specified gain, bandwidth, and input and output impedances. The latter example requires the growth of common-base and common-collector transistors.

The short-circuit collector current of many silicon transistors is proportional to the exponential of the emitter-base voltage over 9 decades of collector current ( 10^{-11} a to 10^{-2} a ). Such a transistor may be connected as a three-terminal feedback network in an operational amplifier to obtain accurate logarithmic transfer response over a dynamic range of 9 decades.

A unified black box approach is presented for synthesizing nonlinear dc circuit models of 3-terminal devices characterized by two families of \upsilon-i curves in piecewise-linear form. In order to model arbitrary curves with nonuniform spacings and slopes, three simple but versatile building blocks-a controlled linear resistance, a controlled concave resistor, and a controlled convex resistor-are introduced and shown to be essential ingredients. The circuit parameters and functions characterizing each element in the black box model can be determined easily from the slopes and breakpoints associated with the segments of the prescribed characteristic curves. The paper concludes with the presentation of several nonlinear dc circuit models for four widely used devices; namely, bipolar transistors, field-effect transistors (FET's), unijunction transistors, and triacs.

This paper is concerned with the problem of simulating transistors operating as switches, or as nonlinear amplifiers, for the IBM Electronic Circuit Analysis Program. A transistor equivalent circuit is developed and then converted into a form that is acceptable in ECAP language. The validity of the developed model is demonstrated by comparing the results of an ECAP analysis of a transistor inverter circuit and the experimentally measured waveforms.

This paper describes some novel circuit design techniques for linear integrated circuits. These techniques make use of elements which can be constructed easily in monolithic form to avoid processing difficulties or substantial yield losses in manufacturing. Methods are shown which eliminate the need for the wide variety of components and tight component tolerances usually required with discrete designs, which substitute parts which can be made simply, and which make use of special characteristics obtainable with monolithic construction.

A new computation method is given connected with the analysis of equivalent circuits including uncorrelated as well as correlated noise sources, thus saving computer time.