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The growing demand for high-performance ultra-high-definition video coding leads to H.265/high-efficiency video coding (HEVC), where the increased computational complexity and data/timing dependence hinder its coding throughput. To address these challenges, this paper presents four algorithm adaptations and a fully parallel hardware architecture for an H.265/HEVC intra encoder. To the best of our knowledge, this is the first fully parallel H.265/HEVC intra encoder. This design supports 35 prediction modes and all coding tree unit partitions. All PUs are independently processed in four prediction engines for high parallelism. An appropriate set of intra prediction modes, RDO candidates, and CABAC rate estimate instances is assigned to each prediction engine, where internal computational tasks are pipelined and scheduled to maximize the processing throughput. Compared with the HM-15.0 software, the proposed algorithm adaptations lead to a reduction of 27% in computational workload, while the average BD-rate and BD-PSNR are 4.39% and −0.21 dB, respectively. This BD-rate is lower than the existing designs with the same video resolution. FPGA implementation of the proposed design shows that it operates at 120 MHz and supports 45 fps of 1080P video sequences using 201-K logic elements and 120-KB on-chip SRAM. ASIC implementation of the proposed design in TSMC 90-nm technology shows that its clock frequency reaches 320 MHz with a hardware gate count of 2288 K, and that it supports real-time encoding of 30 fps of 4-K video sequences. Compared with the state-of-the-art designs, our proposed design demonstrates advantages in computational complexity, bit rate, video quality, throughput, reliability, and flexibility. [ABSTRACT FROM AUTHOR]

High computational complexity and heavy data/timing dependency in high efficiency video coding (HEVC) hinder the throughput of video encoding. In order to address both design challenges, we present high-performance algorithm adaptations and high-throughput hardware architecture for the HEVC intra encoders. Particularly, the chroma intra prediction includes the derived luma mode, which greatly improves the worst-case video compression performance. Compared with the HM-15.0 reference software, the proposed algorithms reduce the computational workload by 22%, while the average BD-Rate and BD-PSNR for classes A-F and 4K are 2.79% and −0.13 dB, respectively. This BD-Rate is lower than existing designs in the literature with the same video resolution. The field-programmable gate array (FPGA) implementation of proposed design shows it operates at 120 MHz and supports 45 f/s of 1080P video sequences using 196K logic elements and 127-KB on-chip SRAM. The application-specified integrated circuit (ASIC) implementation of the proposed design in TSMC 90 nm technology shows that its clock frequency reaches 320 MHz with a hardware gate count of 2186K and power consumption of 290 mW, and it supports real-time encoding of 4K videos at 30 f/s. [ABSTRACT FROM AUTHOR]