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Lines are significant features enclosing high-level information in an image. The line segment Detector (LSD) Algorithm with low error rate is a widely used method to extract lines in images effectively and accurately. However, the algorithm on PC performs too costly both in time and resources for the real-time video processing. This paper provides a fast and resource-efficient hardware implementation solution for a modified LSD algorithm on Field Programmable Gate Arrays (FPGA) for real-time line detection. The task-level pipeline structures are exploited fully in a stream process mapped to the hardware architecture free of frame buffer. Our proposed hardware implementation processes in a stream-in–stream-out manner with little consumption of the on-chip block RAM to store intermediate values. We first employ hardware Gaussian filter and adjust Canny edge detection to obtain an edge map at single-pixel width. Then, a novel structure of region growing model based on dynamic rooted tree is used to detect line segment regions accurately with a latency of only a few rows of pixels. The low cost in time, on-chip resources, and power consumption makes our proposed algorithm suitable for portable real-time streaming video processing applications using line segment features, such as Lane departure warning systems. It can also be applied in real-time machine vision systems that use line segments information for further recognition or stereo correspondence and many others. The proposed algorithm is synthesized and tested on XC7Z020 FPGA with high reliability, accuracy speed, and low cost in both resources and energy. [ABSTRACT FROM AUTHOR]

Image scaling is an important technique that is widely used in many image processing applications. This paper presents a novel scaling algorithm for the implementation of 2-D image scalar. The proposed interpolation method is based on the interpolation error theorem often mentioned in numerical analysis. A bilateral error-amender is used to make the interpolation more precise, and an edge-weighted scheme enhances the edge features of the scaled images. Extensive experimental results demonstrate that the proposed method can obtain better performance than previous methods in both quantitative evaluation and visual quality. This paper also presents an efficient very large-scale integrated architecture for the proposed method. The cooperation and hardware sharing techniques greatly reduce hardware cost requirements. Using a nine-stage pipeline, the proposed scaling circuit contains 13 k gate counts and yields a processing rate of approximately 278 MHz using TSMC 0.13-\mum technology. The hardware cost of the proposed circuit is low, making it a good candidate for high-quality image scaling applications. [ABSTRACT FROM PUBLISHER]

It is very challenging to de-interlace high-definition videos in real time, as both good visual quality and low complexity should be fulfilled, which, however, are conflicting. To resolve the conflict, a syntax-based de-interlacer is proposed specially for H.264-coded videos, by which the values of the syntax elements (SE) in H.264 bitstreams, such as macroblock-type, intra-prediction modes, and motion vectors (MV), are used to detect edge and motion, estimate the MV, and select proper local de-interlacing algorithms accordingly. A verification mechanism is also proposed to make sure the referred SE values are reliable. The experimental results show that the proposed de-interlacer provides better visual quality than common ones and can de-interlace 1080i sequences in real time on PCs. [ABSTRACT FROM PUBLISHER]