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This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

A new scheme of a gain/efficiency-improved serial- parallel switched-capacitor converter (SPSCC) is proposed by combining an adaptive-conversion-ratio (ACR) and pulse-width- modulation (PWM) control for step-up DC–DC conversion. For improving gain, the power part consists of one mc-stage cell and one nc-stage cell in cascade to obtain the step-up gain of (mc+1)\times(nc+1) at most. For improving efficiency, the ACR control with adapting stage number m,n is presented to select a proper gain of (m+1)\times(n+1) (m=1,2,\ldots,mc, n=1,2,\ldots,nc) according to the desired output. Further, the PWM control is adopted to enhance output regulation as well as robustness to source/loading variation. Some theoretical analysis and control design include: formulation, steady-state analysis, conversion ratio, efficiency, output ripple, stability, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a SPSCC prototype, and all results are illustrated to show the efficacy of this scheme. [ABSTRACT FROM PUBLISHER]

An interleaved scheme of variable-conversion-ratio (VCR) multistage switched-capacitor-voltage-multiplier/divider (SCVM/SCVD) converter is proposed by combining a VCR-based phase generator and pulse-width-modulation (PWM) controller to integrate step-up and down modes in one structure for high-efficiency conversion. The power part consists of two mc-stage SC cells (front) and two nc-stage SC cells (rear) in series for step-up/down gain of mc\times nc or 1/(mc\times nc) at most. Here, VCR-based phase generator is suggested with changing the running stage number m,n and topological path to obtain a suitable gain of m\times n or 1/(m\times n) (m=1,2,\ldots,mc, n=1,2,\ldots,nc) for improving efficiency, especially for the lower desired output. Besides, PWM is adopted to enhance output regulation as well as robustness to source/loading variation. Further, some theoretical analysis and design include: formulation, steady-state analysis, conversion ratio, efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed-loop SCVM/SCVD is simulated, and the hardware is implemented and tested. All results are illustrated to show the efficacy of this scheme. [ABSTRACT FROM PUBLISHER]

A new Class-K* audio amplifier with high-power efficiency and high fidelity is integrated in a 0.35-µm CMOS process. It proposes a new topology connected Class-D amplifier with fast-switching charge-dump (FSCD) amplifier in parallel. The integration of the amplifier requires neither analog buffer amplifier nor a complex compensation circuit needed in hybrid audio amplifier (Class-K). The FSCD amplifier composed of comparators and switches works at a high-switching frequency in order to absorb the distortion caused by Class-D amplifier switching. Thus, this assists the audio amplifier to have good linearity under switching operation. With the proposed topology, the audio amplifier has a flat frequency response with 3-dB bandwidth of 60 KHz and is capable of delivering up to 257 mW into 4.1-Ω load with maximum efficiency of 81%. A typical total harmonic distortion plus noise (THD + N) is less than 0.1% at the power level over 25 mW within the audio frequency range (20 Hz--20 kHz), and the minimum THD + N is 0.025% with the audio input frequency of 1 kHz at the output power of 114 mW [ABSTRACT FROM AUTHOR]