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Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics. [ABSTRACT FROM AUTHOR]

A sensor circuit to measure the output power of a dc–dc boost for photo-voltaic (PV) maximum power point tracking (MPPT) application is presented. The proposed approach obviates the need for a series current sense resistor and a complex current/voltage digitization and multiplication circuitry required for calculating power. Thereby, this technique does not require analog multipliers, analog-to-digital converters, digital signal processor, and FPGA, thus reducing the bill of material, silicon area, and power consumption of the overall system. Additionally, it provides the dc electrical isolation between the high output voltage of the boost converter and the low-voltage integrated CMOS power sensor circuit. The proposed power sensor circuit is implemented using a switched capacitor differentiator and a voltage-to-time converter. This approach results in lower complexity, lower silicon area, lower power consumption, and lower component count for the overall PV MPPT system. Designed in a 180-nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes a power of 0.748 mW. [ABSTRACT FROM AUTHOR]

A built-in self-test (BIST) technique that enables tracking of loop parameters of integrated DC–DC converters without affecting the normal mode of operation is presented. A digital pseudo-noise based stimulus and a mixed signal cross-correlation based analysis technique is used to derive on-chip impulse response, with minimum computational requirements in comparison to a digital correlator approach. Using measured impulse response, open-loop phase margin and closed-loop unity-gain frequency are estimated within 5.2% and 4.1% error, respectively, for the load current range of 30 mA to 200 mA. Converter parameters, such as natural frequency, Q -factor, and center frequency are estimated within 3.6%, 4.7%, and 3.8% error, respectively, over load inductance of 4.7 \mu \text{H} to 10.3 \mu \text{H} , and filter capacitance of 200 nF to 400 nF. A 5 MHz switching frequency, 5 V to 8.125 V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed model reference based parametric and non-parametric BIST analysis. The converter output voltage range is 3.3 V to 5 V and supported maximum load current is 450 mA with a peak efficiency of 87.93%. The proposed converter is fabricated on a 0.6 \mu \textm 6 layer-metal SOI technology with a die area of 9 mm2. The system identification circuitry occupies 3.8% of the converter area with 530 \mu \textA quiescent current during operation. [ABSTRACT FROM PUBLISHER]

Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 $\times$ 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits. [ABSTRACT FROM AUTHOR]