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This paper presents a digital battery management unit (BMU) with built-in resistance (BIR) compensation, modulated frequency detection (MFD), and multi-mode protection (MMP) techniques to realize fast, efficient and safe charging. The charger incorporates the proposed BMU based on the low-dropout (LDO) regulator. With BIR compensation, a large rated current in the proposed pulsed constant current (PCC) mode charges the battery, and reduces the charging time by omitting the constant-voltage (CV) mode. The MFD technique allows continuous monitoring and obtains precise BIR compensation with accelerating sampling speed. The MMP technique can alleviate safety concerns while charging, including over-voltage protection (OVP), over-current protection (OCP), and the proposed accidental fluctuation protection (AFP). The digital BMU, implemented in 28 nm CMOS, occupies 0.014 mm2 of silicon area. Experimental results show that the proposed circuit saves 73.3% of charging time with 1.5A charging current, and 21.5% ADC dynamic power with 1A charging current. For the digital controller IC, the power consumption is $59.1~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

A table of contents for the issue is presented including regular papers on various topics such as Analog and Mixed Mode Circuits, Control Theory and Systems and Signal Processing, comments and information for authors.

This paper proposes an LCCC and CCL compensated wireless servo motor control circuitry utilizing the merits of fundamental and third harmonic. With this circuitry, the motor side needs no additional power supply and controller, which significantly reduces the difficulty of maintenance. Besides, benefiting from the proposing of CCL compensating topology and utilizing of the self-driven circuitry, the secondary operates in fully resonant state and the motor direction control H-bridge is self-driven by the LC frequency selecting circuitry (FSC). Moreover, compared with the conventional motor control circuitry, because of the use of fundamental and third harmonic, the power equalization becomes significantly easier, and zero voltage switch (ZVS) can be realized at the same time; Besides, motion direction control of the motor is simpler with only a single pole double throw (SPDT) at the transmitter side. In addition, system resource consumption is reduced compared with conventional motor drive topologies. In this paper, an 180W prototype is built for experimental verification, and the result shows a good power equalization capability and a transfer efficiency reaching up to 90% at the distance of 10cm. [ABSTRACT FROM AUTHOR]

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In the context of global integration, the theory of financial complex networks has made significant contributions to the establishment of stable financial systems and effective regulatory systems. This survey paper presents a systematic methodology for the multi-layer financial complex networks and their applications. Several typical financial networks in existing research are first summarized: the interbank network, the credit network, the international trade network, and the dealer network. The main methods used in the existing literature to analyze the structure of financial networks include maximum entropy methods, network characterization, community detection, and dynamic multi-layer network. Financial risk contagion as well as spillover effects are the core issues that most of the literature focuses on. Finally, this paper reviews the shortcomings of the existing literature and suggests future research directions in this area. [ABSTRACT FROM AUTHOR]

This paper focuses on speeding up NTRU - one of the lattice-based finalists of the NIST PQC competition - by improving the ring multiplication. The Number Theoretic Transform (NTT), Toom-Cook, and Karatsuba are the most commonly used algorithms for implementing NTRU. In this paper, we propose Toeplitz matrix-vector product (TMVP) based algorithms for multiplication for all parameter sets of NTRU. We implement the proposed algorithms on ARM Cortex-M4. The results show that the TMVP-based multiplication algorithms we propose are more efficient than the others in the literature in most cases. Our algorithm for ntruhps2048509 outperform the Toom-Cook and NTT methods in the literature by 25.4% and 21.5%. We also observe the impact of these improvements on the overall performance of NTRU. We speed up the key generation, encryption, decryption, encapsulation, and decapsulation algorithms of ntruhps2048509 by 12.5%, 14.3%, 17.7%, 3.9%, and 14.7%, respectively, compared to state-of-the-art implementation. Moreover, our algorithms require less stack space than the others. [ABSTRACT FROM AUTHOR]

Modern NVIDIA GPU architectures offer dot-product instructions (DP2A and DP4A), with the aim of accelerating machine learning and scientific computing applications. These dot-product instructions allow the computation of multiply-and-add instructions in a single clock cycle, effectively achieving higher throughput compared to conventional 32-bit integer units. In this paper, we show that the dot-product instruction can also be used to accelerate matrix-multiplication and polynomial convolution operations, which are widely used in post-quantum lattice-based cryptographic schemes. In particular, we propose a highly optimized implementation of FrodoKEM wherein the matrix-multiplication is accelerated by the dot-product instruction. We also present specially designed data structures that allow an efficient implementation of Saber key-encapsulation mechanism, utilizing the dot-product instruction to speed-up the polynomial convolution. The proposed FrodoKEM implementation achieves $4.37\times $ higher throughput than the state-of-the-art implementation on a V100 GPU. This paper also presents the first implementation of Saber on GPU platforms, achieving 124,418, 120,463, and 31,658 key exchanges per second on RTX3080, V100, and T4 GPUs, respectively. Since matrix-multiplication and polynomial convolution operations are the most time-consuming operations in lattice-based cryptographic schemes, we strongly believe that the proposed methods can be beneficial to other KEM and signatures schemes based on lattices. [ABSTRACT FROM AUTHOR]

This paper presents a performance analysis of a system for electrochemical impedance spectroscopy (EIS). The system, composed by an analog front-end (AFE) and a custom microcontroller (MCU) board, performs the impulse response (IR) measurement of linear and time-invariant (LTI) systems with pseudo-random excitation signals. As a novelty, a specific AFE for the interfacing of two-terminal resistive and capacitive sensors is covered in detail. The paper proposes, for the first time, a mathematical model to predict the impact of the main noise sources in the measured IR. Thanks to the proposed approach, the AFE and the system’s parameters can be properly designed in order to reduce the error, thus, minimizing the energy-per-error figure of merit (FOM) as well. The AFE is realized as discrete-components circuit and it has been included in a custom MCU-based measurement system as an expansion module. The predicted results from the mathematical model, in terms of noise power, SNR, and measurement error are validated through system-level simulation and experimental measurements. The system performs the IR measurement with 1023 points, showing root-mean-square (RMS) measurement errors of 1% and 1.4% for the tested ADC sampling frequencies of 62.5 kHz and 125 kHz, respectively. These lead to excellent FOM values of 128.9 mJ $\cdot $ %2 and 252.6 mJ $\cdot $ %2 that outstand the state of the art. [ABSTRACT FROM AUTHOR]

This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a $50\times 50$ array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy. [ABSTRACT FROM AUTHOR]

In this paper, the adaptive fuzzy control of switched stochastic nonlinear systems with set-time prescribed performance based on event-driven mechanism is studied. The creative part of this paper is that based on the set-time performance function, a modified event-triggered strategy that considers asynchronous switching to deteriorate system performance without strict assumptions is presented, which avoids Zeno behavior and saves communication resources. Then, by using backstepping recursive design technique, It $\hat {o}$ ’s differential lemma and mode-dependent average dwell time (MDADT) method, a novel adaptive performance control scheme is proposed, which can ensure that all the variables in the system are semiglobally uniformly ultimately bounded (SGUUB) in probability and the tracking error gets into prescribed boundary no later than an arbitrarily adjusted setting time. Finally, the proposed algorithm is applied to a RLC circuit and its practicability is verified via simulation results. [ABSTRACT FROM AUTHOR]

This paper proposes a new approach to above- $f_{max}$ power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/ $\sqrt {\text {Hz}}$ is achieved with the proposed receiver. [ABSTRACT FROM AUTHOR]

Chaotic image encryption is widely used in the field of information security. This paper proposes a novel chaotic image encryption method with spiral-transform-based fractal sorting matrix (STFSM). First of all, the theory of STFSM with good scrambling effect is introduced, which has good irregularity and iterative. Then, the iterative algorithm and calculation example of STFSM are introduced. STFSM can be used as the map of spatial location transformations to implement the design of image encryption. Based on the complete STFSM theory and iterative algorithm, a chaotic image cryptosystem based on STFSM is proposed to achieve a good image encryption process. To test the security of the proposed algorithm, security tests and analyses such as entropy analysis, correlation analysis, resistance to differential attacks analysis, and robustness analysis are used for the proposed algorithm. The experimental analysis illustrates that the algorithm has a better encryption effect, whether using conventional tests or the attacks simulations described in this paper and can also effectively resist the attacks. [ABSTRACT FROM AUTHOR]

For a class of nontriangular nonlinear systems in presence of unknown disturbances, we propose a predictor-based neural dynamic surface control (PNDSC) strategy in this paper. This nontriangular system is transformed via the mean value theorem, and a predictor is then constructed. To avoid an algebraic loop problem, partial state vectors are employed as input signals of neural networks (NNs) for approximating unknown dynamics, and compensation items are designed to compensate for approximation errors from NNs. Different from the traditional NDSC, the PNDSC in this paper utilizes prediction errors to update learning parameters for improving NNs’ learning behaviors with overlarge adaptive gains. On the basis of improved NNs’ approximation behaviors, a predictor-based NNs disturbance observer (PNNDO) is constructed for compensation for external disturbances and approximation errors from NNs. Furthermore, with predictors, a normalization method of weights is developed to reduce the number of online learning parameters. On the basis of the aforementioned result, measurement noises are taken into account in our predictor-based neural control strategy. We employ predictor states, rather than measurement information paralyzed by noises, in design of our control strategy. This reduces high-frequency oscillations in control input. A Lyapunov-based stability analysis shows that all signals are ultimately bounded in the closed-loop system. Finally, the effectiveness of the proposed control strategy is verified by a numerical example and a permanent magnet brushless DC motor system. [ABSTRACT FROM AUTHOR]

This paper is concerned with distributed consensus control of unknown multiagent systems. As the system’s dynamics is unknown, an adaptive Fourier decomposition (AFD) based iterative learning control (ILC) dynamics adaptive matching method in frequency domain is put forward to deal with it. First, large amounts of input and output measurement data are used to estimate the frequency domain characteristics of the system by Takenaka-Malmquist functions. Second, convert the traditional time domain ILC to the frequency domain to establish a matching relationship with the estimated frequency domain features. Then, an adaptive iterative learning rate is constructed to achieve the optimal convergence at each sampling point. The feasibility of the proposed algorithm is guaranteed by the convergence of AFD in Hardy space $H^{2}(\mathbb {D})$ under the maximum selection principle. Compared with the reinforcement learning data-driven control scheme, the method proposed in this paper has obvious advantages in the control accuracy and convergence efficiency. In addition, this paper takes two kinds of denoising algorithms based on unwinding AFD to deal with the multi-agent systems with channel noise. Finally, the feasibility and effectiveness of the developed method are verified by a series of simulations. [ABSTRACT FROM AUTHOR]

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To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH $x2$ programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH $x2$ threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH $x2$ threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH $x2$ threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH $x2$ threshold cell–along with the symmetry of the mask- and field-programmable gate array logic cells–made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric. [ABSTRACT FROM AUTHOR]

In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication [ABSTRACT FROM AUTHOR]

Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are core components in the field of signal processing. However, in the existing research, there is no fully analog circuit that can realize the one-step calculation of FFT. Therefore, in this paper, an analog circuit that can calculate FFT and its inverse transform IFFT in one-step is proposed. First, a circuit that can realize complex number operations is designed. On the basis of this structure, a fully analog circuit that can realize fast and efficient computing of FFT and IFFT in one-step is proposed. In addition, different coefficient matching can be obtained to achieve arbitrary points of FFT and IFFT by adjusting the resistance value of the memristor, which has good programmability. Specific examples are given in the paper to evaluate the proposed method. The PSPICE simulation results show that the average accuracy is above 99.98%. More importantly, the calculation speed has been greatly improved compared with MATLAB simulation. Finally, the proposed circuit can be used to quickly solve convolution operation, and the average accuracy can reach 99.95%. [ABSTRACT FROM AUTHOR]

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of $128\times 128$ (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm2, respectively. [ABSTRACT FROM AUTHOR]

This paper describes a hybrid binary frequency-phase shift keying (BF-PSK) receiver architecture designed with a technique involving both the received signal frequency and phase for low-power operation with relatively high data rate. The method enables the demodulation of the incoming signal without synchronization requirements, which reduces the design complexity and power consumption. The architecture allows programmable data rates and channel bandwidths according to application-specific needs. A novel low-noise amplifier architecture is introduced in this paper as well. The Medical Implant Communication System (MICS) band receiver was designed and fabricated in a standard 65nm CMOS technology, and the measurement results demonstrate the feasibility of this architecture. As a proof-of-concept, it operates with a 416 MHz carrier frequency at a state-of-the-art data rate for sub-milliwatt receivers of 10 Mbps, while consuming $610~\mu \text{W}$ from a 1 V supply. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

Instability and oscillation issues originating in high-voltage direct current (HVDC) systems comprising modular multilevel converters (MMCs) are gaining increasing interest in the research community. To detect such phenomena in advance, considerable effort has been devoted recently to developing MMC models for small-signal analysis. The derivation of such models is a challenging task due to the topology and complex control structure of MMCs, which results in them having a multi-frequency response. To address this issue, scholars developed methods based on dynamic phasors and harmonic state-space modelling, which, however, require extensive pen-and-paper computations. In this paper, the periodic small-signal analysis (PAC) is adopted to determine numerically several MMCs transfer functions. Such functions can be computed between any electrical circuit node or input/output port, without the need to recast the three-phase average MMC model to derive a linear equivalent one, possibly in the DQ-frame. We show how vector fitting allows converting these functions to equivalent algebraic representations, which can be profitably used to design MMCs and study their stability following some parameter changes. To showcase this feature, we exploit one of these transfer functions to detect DC-side instability in a point-to-point HVDC system. [ABSTRACT FROM AUTHOR]

The paper discusses the relationships between electrical quantities, such as voltages, currents, and frequency, and geometrical ones, namely curvature and torsion. The proposed approach is based on the Frenet frame utilized in differential geometry and provides a general framework for the definition of the time derivative of electrical quantities in stationary as well as transient conditions. As a byproduct, the proposed approach unifies and generalizes the time- and phasor-domain frameworks. Other noteworthy results are a new interpretation of the link between frequency and the time derivatives of voltage and current; and a definition of the rate of change of frequency that includes the novel concept of “torsional frequency.” Several numerical examples based on balanced, unbalanced, harmonically-distorted and transient voltages illustrate the findings of the paper. [ABSTRACT FROM AUTHOR]

In this paper, a Takenaka-Malmquist (TM) basis function based equivalent data-model is established by an adaptive rational decomposition for the finite-time interval trajectory tracking control and real-time control of a class of nonlinear systems in the frequency domain. This data model can adaptively learn and match the control process of nonlinear systems. As a result, the proposed trajectory tracking as well as real-time control method can reflect the feature of adaptive learning in order-by-order decomposition, and the feasibility of the proposed method is guaranteed by the convergence of adaptive decomposition by TM basis function under the maximum selection principle (MSP) in Hardy space $H^{2}(\mathbb {D})$. Compared with the traditional model-free control method, this data learning model which matches the control process has obvious advantages in the system model expression and control accuracy. Simulation results at the end of this paper show the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, the distributed optimal containment control problem for multiple nonholonomic mobile robots (NHMRs) differential game is studied via reinforcement learning. An approximation-based optimal control strategy is developed to ensure the optimal performance index and avoid the potential collision among agents. Firstly, the collision avoidance problem considered in this paper is addressed by exploiting a consensus-like interconnection on a directed graph and an error transformation function. Then, on the basis of the optimal backstepping technique, a single critic neural network is adopted to obtain the solution of the coupled Hamilton-Jacobi (HJ) equation, in which an improved learning mechanism is constructed to relax the requirement on initial control conditions. In addition, based on the Lyapunov stability theory, it is proved that all signals in the closed-loop optimal control are uniformly ultimately bounded. Finally, the proposed control protocol is applied to NHMRs system, which verifies that the solution of the coupled HJ equation solves the containment problem of differential game. [ABSTRACT FROM AUTHOR]

Field-Coupled Nanocomputing technologies have great potential to surpass CMOS technology because of their lower power consumption and higher device concentration. To ease the burden of placement and routing (P&R) problems for FCN circuits, many delicate two-dimensional clocking schemes have been proposed, upon which algorithms can solve the P&R problems more strategically. In this paper, we propose a two-level optimization strategy by using a genetic algorithm (GA) combined with an enhanced A* algorithm. Some circuit design requirements, such as clock synchronization, layout area, etc., are cleverly designed in the fitness value function of the GA. Numerical results demonstrate the effectiveness of the hybrid algorithm. In particular, compared to current tools, such as fiction and Ropper, the proposed algorithm can achieve an optimal solution with a higher success rate and a sizeable applicable circuit scale. In addition, the concept of design rule checking (DRC) was proposed in FCN and integrated into the algorithm, making the P&R results mapping from gate-level to cell-level more smoothly. Besides, the number of cross wires is significantly reduced, and the distribution of IO ports can be more effectively controlled. [ABSTRACT FROM AUTHOR]

This paper presents an overview of proximity wireless communication (PWC) technologies, their principles, design guidelines and practical applications. In particular, two different applications of PWC are reviewed. One is PWC between stacked chips. Both communication distance and coupler size are several tens of microns. Area and energy efficient design techniques are introduced. Another is PWC between module boards. Both communication distance and coupler size are several millimeters. Energy and area efficient practical designs are introduced for mobile and industrial machinery applications. [ABSTRACT FROM AUTHOR]

In this paper, based on sampled-data control method, we address the stabilization problem for a general class of linear continuous-time fractional systems whose solution contains the Mittag-Leffler function that does not obey the basic exponentiation identity. By considering the infinite memory and hereditary characteristics of fractional-order calculus, we propose a sampled-data controller that guarantees the resulting closed-loop system to be asymptotically stable. Simulation examples are presented to demonstrate the effectiveness of the proposed controller and verify the established results. [ABSTRACT FROM AUTHOR]

SRAM based computing-in-memory (SRAM-CIM) techniques have been widely studied for neural networks (NNs) to solve the “Von Neumann bottleneck”. However, as the scale of the NN model increasingly expands, the weight cannot be fully stored on-chip owing to the big device size (limited capacity) of SRAM. In this case, the NN weight data have to be frequently loaded from external memories, such as DRAM and Flash memory, which results in high energy consumption and low efficiency. In this paper, we propose a hybrid-device computing-in-memory (HD-CIM) architecture based on SRAM and MRAM (magnetic random-access memory). In our HD-CIM, the NN weight data are stored in on-chip MRAM and are loaded into SRAM-CIM core, significantly reducing energy and latency. Besides, in order to improve the data transfer efficiency between MRAM and SRAM, a high-speed pipelined MRAM readout structure is proposed to reduce the BL charging time. Our results show that the NN weight data loading energy in our design is only 0.242 pJ/bit, which is 289 $\times $ less in comparison with that from off-chip DRAM. Moreover, the energy breakdown and efficiency are analyzed based on different NN models, such as VGG19, ResNet18 and MobileNetV1. Our design can improve $\mathbf {58\times \,\,to\,\,124\times }$ energy efficiency. [ABSTRACT FROM AUTHOR]

The performance of nanoscale semiconductor technologies has become susceptible to high temperatures and aging phenomena. While guard-bands have conventionally been used to combat degradation-induced timing violations, approximations have recently been leveraged to compensate for degradations in lieu of adding timing guard-bands, without a loss in performance. However, only simple approximation techniques such as truncation have been considered in prior work. In this paper, a wide range of approximate arithmetic circuits including adders and multipliers using various sophisticated approximation techniques are investigated to cope with aging- and temperature-induced degradations. To this end, approximate circuits are first characterized for their delay increase under degradations. With this, we then determine the approximation level required to compensate for guard-bands under different degradations. Degradation-aware logic synthesis results show that the simple use of truncated arithmetic circuits leads to a higher quality loss compared to using other approximate circuits. However, a truncated multiplier has the lowest error distance towards a reliable operation in 10 years. The approximate multipliers with configurable error recovery are most suitable when the level of degradation is higher, e.g., at a temperature of 70 °C. The characterization of degradation at the circuit level is then used for design exploration at the architecture level without the need for further gate-level simulations. For three different image processing applications, experimental results show that guard-bands can be mitigated while maintaining an output result with a high visual quality. [ABSTRACT FROM AUTHOR]

This paper presents a novel flexible capacitive power transfer (CPT) system, which has stable output capability when the coupler is deformed. To obtain the flexible coupler structure, the copper foil with the features of light, thin, and cost-efficiency is employed to form the flexible capacitive coupling. To achieve stable output capability, the frequency band selection method and the frequency splitting characteristic are deduced, which indicates that if the system works on optimized natural resonant frequency, moderate deformation of the copper foil coupler could have negligible effects on output power and efficiency. Furthermore, the finite-element analysis (FEA) is employed to simulate the variation of electric field distribution in the flexible coupler. Finally, a prototype is constructed in the laboratory. The copper foil coupler with 60 $\mu \text{m}$ thickness and the dimension of $30\times 16$ cm is adopted, which can achieve more than 147 W power transfer for a 100 mm air gap with the efficiency over 86%. When the bending displacement is within 40 mm, the fluctuations of received power and efficiency are less than 3.6% and 3.1%, respectively. The measured results validate the feasibility of the proposed CPT system for being applied in flexible scenarios. [ABSTRACT FROM AUTHOR]

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{\mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{\mathbf {e}}$ values. Design theories for obtaining the desired $Q_{\mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure. [ABSTRACT FROM AUTHOR]

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB. [ABSTRACT FROM AUTHOR]

This paper focuses on the distributed consensus seeking of multi-agent systems (MASs) with discrete-time control updating and intermittent communications among agents. Compared with existing linearly coupled protocols, a nonlinear coupled Zeno-free event-triggered controller is first proposed, which is further to project the static and dynamic triggering mechanisms exploited by using the deadband control method. Then, the node-based nonlinear coupled adaptive event-triggered controller with online self-tuning of time-varying coupling weight and its corresponding to static and dynamic deadband-based event-triggered mechanisms are designed, respectively. The exploited adaptive event-triggered controller does not rely on any global information of interaction structure and is implemented in a fully distributed fashion. In addition, two dynamic proposals not only cover existing static strategies as special cases, but also show that the minimal inter-execution time of dynamic one is not smaller than that of static one. Theoretical analysis shows that the proposed static and dynamic deadband-based event-triggered mechanisms can not only ensure the average consensus with Zeno-freeness, but also achieve the data reduction of communication and control. Finally, the proposed algorithms applied to circuit implementation are corroborated to prove its practical merits and validity. [ABSTRACT FROM AUTHOR]

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the $\text{V}_{\mathrm {OUT}}$ error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- $\mu \text{V}$ /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations. [ABSTRACT FROM AUTHOR]

Convolution neural network (CNN) with pruning techniques has shown remarkable prospects in electrocardiogram (ECG) classification. However, efficiently deploying the existing pruned neural network to wearable devices for ECG classification is a great challenge due to the limited hardware resource and randomly distributed sparse weights. To address this issue, an efficient unstructured sparse CNN accelerator is proposed in this paper. A tile-first dataflow with compressed data storage format is presented to skip zero weight multiplications and increase the computing efficiency during inference of small-scale model with large sparsity. The two-level weight index matching structure in the dataflow exploits shifting operation to select valid data pairs and maintain the fully-pipelined calculation process. A configurable processing element (PE) array with 32-bit instruction control is proposed to increase the flexibility of the accelerator. Verified in FPGA and post-synthesis simulations in SMIC 40nm process, the proposed sparse CNN accelerator consumes $3.93~\mu $ J/classification at 2MHz clock frequency and it achieves an averaged ECG classification accuracy of 98.99%. A computing efficiency of 118.75% is realized which is improved by 48% compared to the dense baseline. In brief, the proposed efficient CNN accelerator is especially suitable for wearable ECG classification device. [ABSTRACT FROM AUTHOR]

Diffusion-driven instabilities with pattern formation may occur in a network of identical, regularly-spaced, and resistively-coupled cells if and only if the uncoupled cell is poised on a locally-active and stable operating point in the Edge of Chaos domain. This manuscript presents the simplest ever-reported two-cell neural network, combining together only 7 two-terminal components, namely 2 batteries, 3 resistors, and 2 volatile NbOx memristive threshold switches from NaMLab, and subject to diffusion-driven instabilities with the concurrent emergence of Turing patterns. Very remarkably, this is the first time an homogeneous cellular medium, with no other dynamic element than 2 locally-active memristors, hence the attribute all-memristor coined to address it in this paper, is found to support complex phenomena. The destabilization of the homogeneous solution occurs in this second-order two-cell array if and only if the uncoupled cell circuit parameters are chosen from the Edge of Chaos domain. A deep circuit- and system-theoretic investigation, including linearization analysis and phase portrait investigation, provides a comprehensive picture for the local and global dynamics of the bio-inspired network, revealing how a theory-assisted approach may guide circuit design with inherently non-linear memristive devices. [ABSTRACT FROM AUTHOR]

In this paper, we consider the identification problem for nonlinear state-space models with skewed measurement noises. The generalized hyperbolic skew Student’s t (GHSkewt) distribution is employed to describe the skewed noises and formulate the hierarchical model of the considered system. A unified framework for estimating unknown states and model parameters is presented based on expectation-maximization (EM) algorithm, in which the forward filtering backward simulation with rejection sampling (RS-FFBSi) is employed to efficiently estimate the smoothing densities of the hidden states, and optimization method is adopted to update model parameters. One numerical study and the electro-mechanical positioning system (EMPS) are employed to verify the effectiveness of the developed approach. [ABSTRACT FROM AUTHOR]

Computing in memory (CIM) is a promising candidate for high throughput and energy-efficient data-driven applications, which mitigates the well-known memory bottleneck in Von Neumann architecture. In this paper, we present a reconfigurable bit-serial operation using toggle spin-orbit torque magnetic random access memory (TSOT-MRAM) to perform the computation completely in the bit-cell array instead of in a peripheral circuit. This bit-serial CIM (BSCIM) scheme achieves higher throughput and energy efficiency in CIM. First, basic Boolean logic operations are realized by utilizing the feature of TSOT device. A bit-cell array that implements the bit-serial operation is then built to provide the communication between column and row necessary for arithmetic operations, such as the carry propagation of addition and multiplication. Finally, we analyze the reliability of BSCIM scheme and demonstrate the performance advantage by performing convolution operations for $28\times 28$ handwritten digit images in a BSCIM architecture. The results show that the delay and energy of BSCIM architecture are respectively reduced by 1.16-5.49 times and 1.12-1.43 times compared with the existing digital CIM architectures. Besides, its throughput and energy efficiency are also enhanced to 51.2 GOPS and 9.9 TOPS/W respectively. [ABSTRACT FROM AUTHOR]

The DC-DC converter severs as one of the crucial components in DC microgrid applications. In this paper, a novel low frequency current-mode control strategy is proposed to improve overshoot suppression performance for the boost converter against load current and source voltage disturbances. The control strategy is presented as a cascade dual-loop structure composed of a dynamic current-loop controller with asymmetric saturation and a PI form voltage-loop controller. With the low frequency information of disturbances, the designed dynamic current-loop controller delivers not only promising disturbance suppression but also superior reference current tracking. Simulation and experiment results are provided to illustrate the superiority of the proposed strategy on overshoot suppression. [ABSTRACT FROM AUTHOR]

Phase locked loops for fractional frequency synthesis typically use Digital $\Delta \Sigma $ Modulators (DDSMs) as their divider controllers. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of their quantization errors, spur immunity and implementation costs. This paper presents a family of DDSMs that have provably high spur immunity and low folded noise when used in fractional- ${N}$ frequency synthesizers with polynomial nonlinearities. [ABSTRACT FROM AUTHOR]

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with $0.18\mu m$ CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the demodulator is able to demodulate the cycle-by-cycle modulated FSK signals with low modulation index of 2.5%, with a BER of $1.24\times 10^{-5}$. [ABSTRACT FROM AUTHOR]

Single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. More specifically, both MOS and SET devices can be used to implement XOR gates with almost the same area costs regardless of the number of their inputs, outperforming pure CMOS solutions. As multiple-input XOR gates are abundant in the finite field polynomial multiplication which represents the most frequent computation in elliptic curve cryptosystem, hybrid SET-MOS technology can substantially reduce the area cost for this application. This paper presents polynomial multiplication architectures with hybrid SET-MOS transistors and explores Karatsuba-algorithm based multiplication for further area optimization. Simulations show that the proposed hybrid SET-MOS implementations can typically provide around 37% savings in terms of gate count compared to their traditional CMOS counterparts. [ABSTRACT FROM AUTHOR]

In this paper, the digraph filter design based on directed Laplacian matrix (DLM) and least squares method is presented. First, the eigen-decomposition of DLM is used to define the digraph Fourier transform (DGFT). Then, the spectral properties of DGFT are studied and applied to specify the ideal spectral response of the digraph filter. Next, the coefficients of polynomial and rational digraph filters are determined by the least squares method which minimizes the integral absolute squared errors between ideal response and actual spectral response of filter. The matrix inversion can be used to compute the optimal solution. Finally, the proposed method is compared with conventional design methods to evaluate performance and the signal denoising application examples are demonstrated to show the effectiveness of the designed digraph filters. [ABSTRACT FROM AUTHOR]