Search

This article proposes a robust method for the synthesis and design of optimal linear group delay filters with prescribed bandwidth and dispersion properties. The proposed filters are based on a cascade of second-order all-pass filter cells, for which all the parameters are optimized in order to reach the desired wideband linear group delay characteristic with positive slope. Compared to the previously published synthesis method, the proposed approach offers appropriate initialization enabling convergence and aiming for the optimal solution. The method’s convergence and robustness are proved through a 21-cells synthesis, which is the highest number of cascaded cells reported to date, due to the usual convergence problem. Then the electronic feasibility is illustrated through the measurement results of a lumped-elements linear group-delay filter prototype dimensioned with this method. The measured group delay presents a positive slope of 8 ns GHz−1 in the frequency range [100–725] MHz. It is, to the best of our knowledge, the highest positive slope reported to date with an electronic implementation (i.e except SAW and waveguide devices). [ABSTRACT FROM AUTHOR]

CORDIC algorithm is suitable to implement sine/cosine function, but the large number of iterations lead to great delay and overhead. Moreover, due to finite bit-width of operands and number of iterations, the relative error of floating-point sine or cosine is terrible when the input angle is close to 0 or $\pi /2$ , respectively. To overcome these shortcomings, TCORDIC algorithm, which combines low latency CORDIC and Taylor algorithm, is presented. After analyzing the latency of traditional CORDIC, low latency CORDIC is proposed, which adopts the technique of sign prediction, compressive iterations, and parallel iterations. Besides, the calculating boundary ( N$ ), which is used for determining whether Taylor algorithm is selected or not in TCORDIC algorithm, is evaluated to achieve a trade-off between area and delay. Truncated multipliers are used to reduce the area further. Finally, Using TCORDIC algorithm, pipelined and iterative structures are implemented for IEEE-754 double precision floating-point sine/cosine with the input Z\epsilon [0,\pi /2]$ . Under typical condition (1V, 25 °C), our designs are synthesized with 40 nm standard cell library. For a pipelined structure, the frequency is up to 1.70 GHz and area . Frequency decreases to 1.45 GHz for iterative structure, but the area requires only 110590.81~\mu {\mathrm { m}}^{2} . TCORDIC is efficient in controlling relative error, and achieves the accuracy within one ulp (unit in the last place) for floating-point sine/cosine function. [ABSTRACT FROM AUTHOR]