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This paper presents a nonlinear analytical model for an inverter-based switched-capacitor Class-D RF power amplifier (SCDPA). The root causes of the SCDPA AMAM and AMPM nonlinearities are studied. The major factors affecting SCDPA nonlinearities are identified as the unequal on-resistances of selected cell and unselected cell. Specifically, time-varying resistance of the switch, different transistor responses during the transition and parasitic resistance on the supply path (IR drop) are analyzed. Then, the system-level result, like EVM and power spectral density, can be obtained with nonlinear behavior of PA. The results of model calculation, schematic simulation, and measurement are presented and compared with validate the model both on transistor level and system level. This paper, for the first time, provides an accurate design guidance to enable fast architecture study and quick circuit-level prototype with close-to-optimum component initial parameters. It can be expanded to more architectures, therefore helps to pave the path to future design automation for highly linear SCDPAs. [ABSTRACT FROM AUTHOR]

In the memristive version of a standard space-invariant Cellular Nonlinear Network, each cell accommodates one first-order non-volatile memristor in parallel with a capacitor. In case, the resistance switching memory may only undergo almost-instantaneous switching transitions between two possible resistive states, acting at any time, as either the on or the off resistor, the processing elements effectively operate as first-order dynamical systems, and the classical Dynamic Route Map technique may be applied to investigate their operating principles. On the contrary, in case the memristors experience smooth conductance changes, as the bioinspired array implements memcomputing paradigms, each cell truly behaves as a second-order dynamical system. The recent extension of the Dynamic Route Map analysis tool to systems with two degrees of freedom constitutes a powerful technique to investigate the nonlinear dynamics of memristive cellular networks in these scenarios. This paper exploits this system-theoretic technique, called Second-Order Dynamic Route Map, to introduce a novel systematic procedure to design memristive arrays, in which a given memcomputing task is executed by ensuring that, depending upon the network inputs and initial conditions, the analogue dynamic routes of the states of the processing elements, namely capacitor voltages and memristor states, asymptotically converge toward pre-defined stable equilibria. [ABSTRACT FROM AUTHOR]

This paper presents the design of integrated boost and buck switched-capacitor power converters with high efficiency and fast start-up time. An analysis method is determined to evaluate the key performance parameters of integrated power converters, and techniques are proposed to improve the energy conversion efficiency and the dynamic response. Boost and buck structures are modeled and compared in static and transient conditions, including the losses due to parasitic elements. A switch bootstrapping technique prevents short-circuit losses, improves driving capability and start-up time, and enhances the overall efficiency. Moreover, the application of a charge-reuse technique reduces the dynamic power losses of the integrated structures. Prototypes of the integrated power converters were fabricated in a 180-nm CMOS process. Measurement results based on the proposed techniques are presented, demonstrating the improvements in steady-state and transient characteristics with a good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

In this paper, a novel thermoelectric energy harvesting system with a reconfigurable array of thermoelectric generators (TEGs), which requires neither an inductor nor a flying capacitor, is proposed. The proposed architecture can accomplish maximum power point tracking (MPPT) and voltage conversion simultaneously via the reconfiguration of the TEG array, and demonstrate significantly improved power conversion efficiency over the conventional switching converter and switched-capacitor architectures. Two systematical scaling approaches—powers-of-two scaling and maximum-factor scaling—are presented and analyzed to serve as the design guideline, catering for reconfigurable TEG arrays of different sizes. In order to optimize the chip area required, a custom-designed, multi-level hierarchy and systematically scalable switch array that requires a reasonable number of switches is also developed to enable the reconfiguration of the TEG array. The 16-node and 12-node versions of the proposed system have been implemented in a standard 0.35- \mu \textm CMOS process. Measurement results verify the analysis, and confirm that the proposed system can maintain a higher than 88.8% efficiency over a wide range of temperature gradients. [ABSTRACT FROM PUBLISHER]

A frequently occurring subcircuit consists of a loop of a resistor (R), a field-effect transistor (FET), and a capacitor (C). The FET acts as a switch, controlled at its gate terminal by a clock voltage. There may be many such identical circuits connected in parallel, each driven by a different phase of the clock. This subcircuit may be acting as a sample-and-hold (S/H), as a passive mixer (P-M), or as a bandpass filter or bandpass impedance. In this work, we will present a useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. The SFG dissects the circuit into three filtering functions and ideal sampling. This greatly simplifies analysis of frequency response, noise, input impedance, and conversion gain, and leads to guidelines for optimum design. The analysis is extended to multi-path realizations common in RF applications. Part I of this paper focuses on the analyses of a single-path FET-R-C circuit's signal transfer characteristics. Part II extends these analyses to multi-path FET-R-C circuit configurations, which is followed by the noise and driving-point impedance analyses. [ABSTRACT FROM AUTHOR]

In this paper the power losses of efficient capacitive converters with multitude transfer ratio values are discussed. The loss mechanism circuits, based on general transposed series parallel (GTSP) topology, is studied and the losses are calculated, which in turn enables the “bottlenecks” to be identified and overcome. The calculations show that for a given number of switching cells the power losses of such converters are mainly dependent on the voltage conversion ratio, the topology function, the resistances of the switches in on and off states, the ESR of the capacitors, the switching frequency, the voltage drop, and the load. The theory explains the fact that was observed in experiments, that for low voltage conversion ratio values, efficiency decrease was measured. It is shown that for these low voltage ratio values the mechanism associated to the off resistance of the switches is more dominant and reduces the efficiency. This power loss estimation can be used as a powerful tool for the performance optimization of capacitive converters. The theoretical results are verified experimentally on a 10-cell GTSP converter prototype. The experimental results show good agreement with the proposed theory. [ABSTRACT FROM PUBLISHER]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

A third-order passive switched-capacitor low-pass filter is presented together with experimental results. The current input-voltage output filter structure realizes complex-conjugate poles although it is composed of switches and capacitors. The results are verified with measurements performed on the filter prototype integrated in a 0.13- $\mu \text{m}$ CMOS technology. The prototype has a cut-off frequency of 470 kHz, 150- $\mu \text{W}$ power consumption from 1.2-V power supply, 92-dB SFDR, and an active area of 0.06 mm2. The switch-capacitor filter was obtained using a continuous-time model that is also described here and is useful for design, analysis, and simulation of oversampled switched-capacitor circuits. The model is applicable to a variety of topologies including multi-phase passive switched-capacitor filters, switched-capacitor integrators, as well as switched-capacitor dc/dc converters. [ABSTRACT FROM AUTHOR]

We introduce the cyclic switched-capacitor dc–dc converter for single-input multiple-output power delivery. We focus on applications in stacked voltage domain (SVD)-based systems, and show that the cyclic architecture is robust to load current mismatches. We analyze such converters and give intuition for their power losses. We give experimental results from an SVD based power management integrated circuit (PMIC), designed and fabricated in a 130nm CMOS technology. The PMIC is a combination of a 2/3 stage reconfigurable cyclic SC dc–dc converter and a linear regulator. It can drive $3\times 3$ mA loads with the input supply voltage varying from 2.35–3.65V. [ABSTRACT FROM AUTHOR]