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This paper presents a full hardware implementation of the eXtended Merkle Signature Scheme (XMSS), a NIST approved and IETF RFC specified post-quantum cryptography (PQC) algorithm. An optimized node traversal is proposed to enable efficient memory utilization without compromising the computational latency of the L-tree and Merkle tree construction, which are two key components used for the compression of the Winternitz One-Time Signature (WOTS) public key in XMSS. The computation of the authentication path during signature generation has also been significantly sped up by our proposed hardware implementation of the Buchmann, Dahmen, and Schneider (BDS) algorithm. Our implementation has completely avoided the use of block random-access memory, which is known to be vulnerable to side-channel attacks. The memory requirement has been highly optimized for implementation with small flip-flop chains and register counters as pointers for fast data access. To the best of our knowledge, this is the first full hardware implementation of all three key generation, signing and verification operations of XMSS. The design has been prototyped and evaluated on a 28 nm FPGA platform to demonstrate its performance improvements over the most efficient software and hardware/software co-design methods reported to date. Specifically, it increases the computational efficiency of the best reported XMSS implementation for key generation and signature generation by about 20% and 50%, respectively. It can also run at 10% higher clock speed than the fastest hardware implementation of signature verification in FPGA with 8% lower hardware resource utilization. [ABSTRACT FROM AUTHOR]

Large scale quantum computers will break classical public-key cryptography protocols by quantum algorithms such as Shor’s algorithm. Hence, designing quantum-safe cryptosystems to replace current classical algorithms is crucial. Luckily there are some post-quantum candidates that are assumed to be resistant against future attacks from quantum computers, and NIST is considering standardizing them. Among these candidates, lattice-based cryptography sounds more interesting than others due to the performance results as well as confidence in the security. There are few works in the literature evaluating the performance of lattice-based cryptography in hardware. In this paper, we focus on Cryptographic Suite for Algebraic Lattices (CRYSTALS) key exchange mechanisms known as Kyber and provide an instruction-set hardware architecture and implement on Xilinx Artix-7 FPGA for performance evaluation and testing. Our proposed architecture provides an efficient and high-performance set of components to perform polynomial sampling, number-theoretic transform (NTT), and point-wise multiplication to speed up lattice-based post-quantum cryptography (PQC). This architecture implemented on ASIC outperforms state-of-the-art implementations. [ABSTRACT FROM AUTHOR]

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm. [ABSTRACT FROM AUTHOR]

With the advent of technology over the recent years, the low-density parity-check (LDPC) codes, which were once seen as an impractical concept, are now poised to be the next big thing in the communication standards of today for their near-capacity performances. Nonetheless, the physical implementation of LDPC decoders is more often than not encumbered by the arithmetic of its decoding algorithm. Entangled by numerous computations of minima, LDPC decoders not only require considerable amount of resources to the implement cascaded pair-wise comparators, but also yield low decoding throughputs. In this paper, we propound a novel design for the computation of minimum and subminimum in LDPC decoding, known as the cognitive-amplification detector (CAD). By leveraging on the finite precision of fixed-point binary representation in actual hardware, our CAD proposition renders significant gains in decoding throughput and savings in resource consumption of up to 20% and 15%, respectively, not to mention negligible trade-offs in error-correcting capabilities. [ABSTRACT FROM AUTHOR]

This paper presents a novel hardware architecture for adaptive systems whose exact specification is unknown. The architecture is suitable for linear and nonlinear systems whose inputs are real or complex signals (variables), and that have an acceptable representation as low order polynomials in these variables. The implementation is based on using an a priori selected subset of Walsh spectral coefficients. The proposed architecture can acquire its target functionality and adapt itself to changing environments even if the number of variables, their order and precision are unknown in advance. This is in contrast to conventional multiply-and-accumulate (MAC) based architectures where this information must be determined before the design and implementation of the system. In this context (of systems whose functionality is unknown), the delay and the implementation cost of the proposed architecture is significantly lower than MAC-based solutions. [ABSTRACT FROM AUTHOR]

The Supersingular Isogeny Key Encapsulation mechanism (SIKE) is the only post-quantum key encapsulation protocol based on elliptic curves and isogeny maps between them. Despite the quantum security of the protocol, SIKE requires a greater number of clock cycles and hence does not provide competitive timing and energy consumption results. However, it is more attractive offering the smallest public key as well as ciphertext sizes, which considering the impact of the communication costs and storage of the keys could become a good fit for resource-constrained devices. In this work, we present the fastest practical implementation of SIKE, targeting the platform Cortex-M4 based on the ARMv7-M architecture. We performed our measurements on the STM32F407VG microcontroller for benchmarking the clock cycles and on Nucleo-F411RE attached to X-NUCLEO-LPM01A (Power Shield) for measuring the energy consumption of the protocol. The low-level finite field arithmetic operations play main role in determining the efficiency of SIKE. Therefore, we mainly focus on their optimization and apply them to all NIST-required security levels. Our SIKEp434 implementation for NIST security level 1 is about 22.97% faster than the counterparts appeared in Seo et al. (2020), where for the SIKEp503, SIKEp610 and SIKEp751 the speedup reaches 21.10%, 19.21% and 19.08%. Finally, we benchmark energy consumption and report optimization of up to 11.9% depending on the NIST security level implementation. [ABSTRACT FROM AUTHOR]

We outline a model of computing with high-dimensional (HD) vectors—where the dimensionality is in the thousands. It is built on ideas from traditional (symbolic) computing and artificial neural nets/deep learning, and complements them with ideas from probability theory, statistics, and abstract algebra. Key properties of HD computing include a well-defined set of arithmetic operations on vectors, generality, scalability, robustness, fast learning, and ubiquitous parallel operation, making it possible to develop efficient algorithms for large-scale real-world tasks. We present a 2-D architecture and demonstrate its functionality with examples from text analysis, pattern recognition, and biosignal processing, while achieving high levels of classification accuracy (close to or above conventional machine-learning methods), energy efficiency, and robustness with simple algorithms that learn fast. HD computing is ideally suited for 3-D nanometer circuit technology, vastly increasing circuit density and energy efficiency, and paving a way to systems capable of advanced cognitive tasks. [ABSTRACT FROM PUBLISHER]

To the best of our knowledge, we present the first hardware implementation of isogeny-based cryptography available in the literature. Particularly, we present the first implementation of the supersingular isogeny Diffie-Hellman (SIDH) key exchange, which features quantum-resistance. We optimize this design for speed by creating a high throughput multiplier unit, taking advantage of parallelization of arithmetic in \mathbb Fp^{2} , and minimizing pipeline stalls with optimal scheduling. Consequently, our results are also faster than software libraries running affine SIDH even on Intel Haswell processors. For our implementation at 85-bit quantum security and 128-bit classical security, we generate ephemeral public keys in 1.655 million cycles for Alice and 1.490 million cycles for Bob. We generate the shared secret in an additional 1.510 million cycles for Alice and 1.312 million cycles for Bob. On a Virtex-7, these results are approximately 1.5 times faster than known software implementations running the same 512-bit SIDH. Our results and observations show that the isogeny-based schemes can be implemented with high efficiency on reconfigurable hardware. [ABSTRACT FROM AUTHOR]

In the literature, the generalized $(a, b)$- way Karatsuba algorithm (KA) is a well-known high-precision technique for implementing a subquadratic digit-serial multiplication. We present here the corrections to the space and complexities pertaining to addition operations in $(a, b)$-way KA approach. [ABSTRACT FROM PUBLISHER]

Three distinct methods of reading multi-level cross-point resistive states from selector-less RRAM arrays are implemented in a physical system and compared for read-out accuracy. They are: the standard, direct measurement method and two methods that attempt to enhance accuracy by computing cross-point resistance on the basis of multiple measurements. Results indicate that the standard method performs as well as or better than its competitors. SPICE simulations are then performed with controlled amounts of non-idealities introduced in the system in order to test whether any technique offers particular resilience against typical practical imperfections such as crossbar line resistance. We conclude that even though certain non-idealities are shown to be minimized by different circuit-level read-out strategies, line resistance within the crossbar remains an outstanding challenge. [ABSTRACT FROM PUBLISHER]