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This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a $50\times 50$ array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on the high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation) without needing a detailed electrical simulation. Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, MDM Laboratory. The parameters extraction procedure is also discussed. The obtained results clearly show that the model proposed in this paper is able to capture the influence of the programming pulse parameters (i.e. pulse duration and height) changes. This is accomplished by the introduction of a parameter, which is related to the specific device technology. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) with large scales of artificial neurons are increasingly used in recognition and classification tasks. In power-constrained scenarios, the tradeoff between performance and hardware consumptions must be carefully evaluated before silicon tape-out. In this paper, we proposed a systematic approach to design ultra-low power NN system. This work is motivated by the facts that NNs are resilient to approximation in many of the computations and NNs are outputting statistical tensors which are acceptable to less-than-perfect results. We resort to the front-back end approach with a twofold aim: (1) a fast and accurate design approach is proposed by estimating the computing quality of low-power approximate adder arrays, and it is adopted to evaluate the neural network system; (2) a quality configurable engine with different approximation degrees while processing NNs is implemented. The proposed work is demonstrated with a comprehensive keyword spotting (KWS) system as an ultra-low power NN engine. The experimental environment is setup with ten keywords from the google speech command dataset (GSCD) using an industrial 22-nm ultra-low-leakage (ULL) process. Comparing to the state-of-the-art KWS processors, the proposed approximate NN engine can demonstrate over 60% improvement in power efficiency and $1.1\times $ area efficiency while achieving similar recognition accuracy. [ABSTRACT FROM AUTHOR]

The dynamics of modern hybrid power systems are characterized by behaviors at different timescales, typically separated by several orders of magnitude. In this paper we apply the envelope-following method to hybrid power systems simulations, in which single-phase and three-phase representations of a power system co-occur. This simulation method is well suited for handling coexisting behaviors occurring at different timescales. Compared to the simulation approaches present in the literature, the envelope-following method does not need to continuously switch between two separate simulation engines, but rather automatically handles instantaneous variations in the dynamics of the system, such as faults or topology changes. Additionally, given the vast penetration of power electronic components in modern electricity networks, employing the envelope-following method allows using a vast array of numerical algorithms that have been developed over the years to simulate electrical and electronic circuits. The proposed approach is validated by means of power systems case studies of increasing complexity. [ABSTRACT FROM AUTHOR]

Recently, there have been many studies attempting to take advantage of advancements in Artificial Intelligence (AI) in Analog and Mixed-Signal (AMS) circuit design. Automated circuit sizing optimization and improving the accuracy of performance models are the two predominant uses of AI in AMS circuit design. This paper first introduces and explains the basic concepts in AI especially the ones that are more suitable to this application. Next, it surveys some recent studies of various AI techniques for AMS circuit design. Then, it discusses the main approaches as well as the pros and cons of each method. Finally, it gives meaningful insights about the current challenges and open issues, as well as recommends approaches for specific applications. [ABSTRACT FROM AUTHOR]

In this paper, we present an approach to nonlinear system approximation, called the lattice trajectory piecewise linear (LTPWL) model. The approach involves determining a lattice piecewise linear (PWL) approximation to the state trajectory of a nonlinear system. It has been shown in the literature that the lattice PWL expression can represent any PWL function in any dimension. After the LTPWL approximation has been obtained, the order of each model piece is reduced using a Krylov projection technique. Compared to existing trajectory piecewise linear (TPWL) models, which are quasi-PWL in the whole region, LTPWL models are virtually linear in each subregion. Besides, the single output LTPWL model can be seen as a special kind of TPWL model, in which only one weight is 1, and the other weights are 0. In general, for multiple output LTPWL model, the weights set to be 1 for each component are different, which makes the LTPWL model more flexible in approximation of nonlinear function. The proposed strategy is applied to simulate diode circuits, and the experimental results show that the performance of the LTPWL model is better than that of the traditional TPWL model in terms of approximation accuracy and generalization ability. [ABSTRACT FROM AUTHOR]

This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model. [ABSTRACT FROM AUTHOR]

One of the main causes of expensive IC redesigns is a failure to meet electromagnetic compatibility (EMC) requirements. For this reason, there is a huge demand for verification methods to identify and prevent immunity failures on chip. Strongly nonlinear effects, in particular DC operating point shifts, are a major cause of such immunity failures. Conventional analysis techniques, used to simulate these strongly nonlinear effects, suffer from a few drawbacks. They can be time-consuming and suffer from convergence issues. Moreover, they do not provide insight into the root causes of the nonlinear behavior. In this paper, an automated method is proposed that overcomes the mentioned drawbacks and identifies causes of immunity failures by listing critical distortion contributions. The method is applicable to very large, strongly nonlinear integrated circuits. It uses a simple model that determines the nonlinear contribution of one device in its linearized environment. Because the computation time is negligible, the analysis can be repeated for many devices and interference frequencies. Additionally, the method gives insight into the drivers responsible for the distortion effects, such that the designer can efficiently solve the problem. The method is demonstrated by applying it to a practical test case. [ABSTRACT FROM AUTHOR]

This paper introduces rational polynomial chaos expansions for the stochastic modeling of the frequency-domain responses of linear electrical networks. The proposed method models stochastic network responses as a ratio of polynomial chaos expansions, rather than the standard single polynomial expansion. This approach is motivated by the fact that network responses are best represented by rational functions of both frequency and parameters. In particular, it is proven that the rational stochastic model is exact for lumped networks. The model coefficients are computed via an iterative re-weighted linear least-square regression. Several application examples, concerning both lumped and a distributed systems, illustrate and validate the advocated methodology. [ABSTRACT FROM AUTHOR]

This paper presents a systematic methodology for the co-design of matching network and rectifier of radio frequency (RF) harvesters that results in maximum power conversion efficiency (PCE) for a given available power. This method is based on our newly developed rectifier model capable of calculating the CMOS Dickson’s rectifier’s input/output voltages at a given input power developed for low/high input power regimes. The proposed model allows for the co-design of the matching network and the rectifier in a fraction of time that takes for the design of the RF energy harvester using previously developed models relying on the knowledge of rectifier’s input voltage levels where a computationally extensive iterative design procedure must be performed because of the interdependence of the rectifier’s input voltage, the input power, and the matching network’s and rectifier’s parameters. The proposed methodology is capable of accurately predicting matching network components’ sizes for both the lossless and lossy matching networks for a maximum power transfer. Utilizing the proposed methodology, the designers can produce efficiency contour plots for a given input power for finding the optimum matching network and rectifier’s parameters for maximum PCE. The model, simulation, and measurement results for different parameters and input power levels in a 130-nm process are in good agreement. [ABSTRACT FROM AUTHOR]

The computation-intensive circuit simulation makes the analog circuit sizing challenging for large-scale/complicated analog/RF circuits. A Bayesian optimization approach has been proposed recently for the optimization problems involving the evaluations of black-box functions with high computational cost in either objective functions or constraints. In this paper, we propose a weighted expected improvement-based Bayesian optimization approach for automated analog circuit sizing. Gaussian processes (GP) are used as the online surrogate models for circuit performances. Expected improvement is selected as the acquisition function to balance the exploration and exploitation during the optimization procedure. The expected improvement is weighted by the probability of satisfying the constraints. In this paper, we propose a complete Bayesian optimization framework for the optimization of analog circuits with constraints for the first time. The existing GP model-based optimization methods for analog circuits take the GP models as either offline models or as assistance for the evolutionary algorithms. We also extend the Bayesian optimization algorithm to handle multi-objective optimization problems. Compared with the state-of-the-art approaches listed in this paper, the proposed Bayesian optimization method achieves better optimization results with significantly less number of simulations. [ABSTRACT FROM PUBLISHER]

This paper is concerned with a method for design and analysis of specific neuronal networks, called central pattern generators (CPGs), which produce primary rhythmic patterns in animals. In particular, the paper is focused on synthetic CPGs made up of few basic elements and governing quadrupeds’ gaits and gait transitions, under the control of an external drive. The method combines the principles of bifurcation theory, geometric properties of symmetry, and numerical analysis based on the recently proposed toolbox CEPAGE. The method is applied to two CPGs, one bio-inspired and one purely synthetic. In both the cases, the method provides a way to obtain a desired sequence of gaits by continuously changing a bifurcation parameter related to the external drive. [ABSTRACT FROM AUTHOR]

This paper introduces two statistical delay-variability models for certain hardware adder implementations, namely, the ripple-carry adder (RCA) and the borrow-save adder (BSA). The introduced models take into account correlated variation sources. Initially, we derive a first proposed model, namely, Type-I model, in the form of expressions for the computation of the exact probability density functions (pdfs) of maximum output delays for Gaussian and non-Gaussian variation sources. Furthermore, we present closed formulas for the covariances between output delays of the aforementioned adder architectures. The introduced derived covariances are subsequently combined with Clark’s method to derive a second proposed model, Type-II model, which comprises approximations of the maximum delay pdfs for an RCA and a BSA. Simulation results and the derived exact Type-I PDFs are found to perfectly agree, while the proposed Clark-based Type-II models present an error for standard deviation of maximum delay that increases as BSA word length increases. Both the introduced models and the simulations prove that BSAs achieve narrower delay distributions than RCAs, i.e., they significantly reduce delay variance. Consequently, BSAs are proven to be suitable for variation-tolerant applications by providing a timing safety margin, when compared to RCA architectures. The underlying analysis indicates that for the case of BSA and either intra-die delay variations only or both intra- and inter-die delay variations, the Type-II models introduce non-negligible errors, which are as much as 16% of the standard deviation of maximum delay for a 256-digit BSA, as the Type-II Gaussian pdf approximations deviate significantly from the exact Type-I PDFs. However, for all RCA and BSA inter-die only variation cases, both types present satisfactory accuracy due to the Gaussian shape of exact pdfs. [ABSTRACT FROM AUTHOR]

Large-scale simulation of spiking neural networks on hardware with a remarkable resemblance to their mathematical models is a key objective of the neuromorphic discipline. This issue is, however, considerably resource-intensive due to the presence of nonlinear terms in neuron models. This paper proposes a novel uniform piecewise linear segmentation approach for nonlinear function evaluations. Employing the proposed approach, we present a uniform-segmented adaptive exponential neuron model capable of accurately producing various responses exhibited by the original model and suitable for efficient large-scale implementation. In contrast to previous nonuniform-segmented neuron models, the proposed model enjoys a high-speed and extremely simple segment address encoder unit regardless of the number of segments. Simulations and hardware implementations on FPGA confirm that the proposed model significantly outperforms previous works in terms of resource utilization, accuracy, and maximum clock frequency. Moreover, employing the resource sharing technique, a fully pipelined hardware-efficient network containing one neuron circuit is proposed aimed at simulating a large number of neurons in both real and accelerated time scales. To assess the performance of the proposed network as a high-speed accelerator, four networks composed of 1k to 4k neurons are simulated using both FPGA and standard PC workstation. Results demonstrate that the proposed fully pipelined network accelerates the simulation process, on average, 89.96 times compared with the computer-based simulation. [ABSTRACT FROM AUTHOR]

The technology for oxide resistive memories offers nowadays a number of different implementations and solutions. As a consequence, many models have been presented so far, generally technology-specific, representing a problem for the memory design standardization. Moreover, the computational effort can be reduced using memristive models with lower complexity but that grant at the same time good speed and numerical stability. In this paper, the authors try to find a compromise between accuracy and computational costs, proposing a simulation procedure based on a linear approximation of the memristive device model. The description, formally derived from the traditional linear model, has been implemented in Verilog-A and, thanks to the analysis of practical design cases on a reference architecture, has been demonstrated to be useful in highlighting critical parasitic effects related to the interaction of the memristive cells with the memory circuit periphery. Thanks to the approximated method, a computer simulation time saving up to 40% is achieved when simulating a full cross-bar memory device. The model parameters have been extracted from experimental curves obtained from HfO2 devices implemented in a 250-nm BiCMOS IHP technology. [ABSTRACT FROM AUTHOR]

The wave digital filter (WDF) technique derives digital filters from analog prototypes that classically have been restricted to passive circuits with series/parallel topologies. Since most audio circuits contain active elements (e.g., op-amps) and complex topologies, WDFs have only had limited use in virtual analog modeling. In this paper, we extend the WDF approach to accommodate the unbounded class of non-series/parallel junctions which may absorb linear multiports. We present four modified-nodal-analysis-based scattering matrix derivations for these junctions, using parametric waves with voltage, power, and current waves as particular cases. Three derivations afford implementations whose cost in multiplies are lower than multiplying by the scattering matrix. Negative port resistances may be needed in WDF modeling of active circuits, restricting the WDF to voltage or current waves. We propose two techniques for localizing this restriction. Case studies on the Baxandall tone circuit and a “Frequency Booster” guitar pedal demonstrate the proposed techniques in action. [ABSTRACT FROM AUTHOR]

The simulation of the full netlist of a phase locked loop (PLL) is resource demanding due to the prohibitive time needed to derive output noise, spurs, and transient performance from detailed transistor-level simulations. To overcome this limitation, behavioral models are needed but they must be accurate and time-efficient. This paper introduces a new behavioral macro-model of the charge-pump PLL, addressing both spectral analysis and lock-in transient computation. To meet both accuracy and simulation efficiency, the model accounts for the time-variant transfer of noise and disturbances, and a novel procedure is introduced to extract the model parameters via transistor-level periodic steady-state simulations. To describe the nonlinear dynamics, the model also includes the voltage-controlled oscillator and charge-pump nonlinear characteristic computed via transistor-level simulations. The proposed macro-model has been tested on a 2.765-GHz PLL, and the results are compared against the noise transient simulation of the PLL full netlist. Phase noise and amplitude of spurious tones, both inherently generated and induced by external disturbances, are predicted within ±2 dB. Lock-in transients are also described with an accuracy within a few percent. On the other hand, the simulation time reduction is two/three orders of magnitude for both spectral analyses and transient simulations, depending on the PLL parameters. [ABSTRACT FROM PUBLISHER]

In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is based on one-time characterization via micromagnetic multi-domain simulations, overcoming the inaccuracies introduced by single-domain analysis, which most of the existing frameworks are based on. As further distinctive capability, non-Gaussian stochastic variations of the MTJ write switching time are explicitly modeled through a Skew Normal distribution, making the model suitable for low-power and low-voltage designs. The framework involves the use of a Verilog-A look-up table-based model, which assures easy integration with commercial design tools. Our strategy is evaluated on a spin-transfer torque-magnetoresistive random access memory (MRAM) working in RAM and true random number generator (TRNG) modes. In RAM mode, while the commonly-used approach based on Gaussian-distributed switching statistics tends to underestimate the pulse width required for a write error rate of 10^-6 by about 20%, our Skew Normal-based strategy allows tracking reference micromagnetic results with an average error less than 4%. In TRNG mode, our approach also allows a better tracking of the reference 50%-switching probability contour with an error less than 1%abs. However, the incorporation of the Skew Normal distribution in our Verilog-A model results in an increase of the CPU time by 50% on average as compared with the use of the built-in statistical functions. [ABSTRACT FROM AUTHOR]

Memory-centric computing with on-chip non-volatile memories provides unique opportunities for native and local information processing in an energy-efficient manner. Design and modeling methodology based on resistive random access memory (RRAM) is presented in this paper. A hierarchical RRAM SPICE model having different levels of physics realism is described, where the incorporated stochasticity provides a more accurate representation of RRAM operations. Three in-memory operation schemes are developed and experimentally verified for reconfigurable in-memory logic, using RRAM built in 3-D vertical structure (i.e., 3-D RRAM). As a case study for RRAM-centric computing systems, we evaluate the Please note that there were discrepancies between the accepted pdf [TCAS_R1_combined.pdf] and the [TCAS_RRAM-centric computing_hli_FINAL_submit.docx] in the lines 12 and 70. We have followed [TCAS_RRAM-centric computing_hli_FINAL_submit.docx]. use of 3-D RRAMs for a language recognition system using the hyperdimensional (HD) computing model. Utilizing the inherent properties of 3-D RRAM, we demonstrate, using fabricated 3-D RRAM integrated with FinFET, the essential kernels for HD operations: multiplication, addition, and permutation (MAP). RRAM-centric HD systems exhibit strong resilience to hard errors induced by RRAM endurance failures, making a promising case for using various types of RRAM for memory-centric HD systems. [ABSTRACT FROM PUBLISHER]

Analog matrix computing (AMC) with resistive memory implies naturally massive parallelism and in-memory processing, thus representing a promising solution for accelerating data-intensive workloads in many applications. In AMC circuits, the interconnect resistances residing in the crosspoint resistive arrays arise as a main non-ideal factor degrading the computing accuracy. Simulating and optimizing the circuits are of fundamental importance for large system integration. In this work, we develop a physics-based iterative algorithm to quickly model the matrix-vector multiplication (MVM) operation of crosspoint resistive array with interconnect resistances, thus quadratically reducing the time complexity of circuit simulation. In addition, we propose a new MVM circuit for matrix with negative values, in parallel with the conventional column-wise splitting (CS) and row-wise splitting (RS) circuits. The circuit is based on the conductance compensation (CC) strategy to realize a simplified RS scheme. The discrete Fourier transform (DFT) is implemented using this circuit as a case study. Simulation results reveal that the computing error caused by interconnect resistances is remarkably reduced in the CC-RS circuit. Also, the CC-RS scheme is demonstrated to be more immune to device variations and source/sink resistances. Our results provide an efficient modeling method together with an optimized approach for AMC circuits with non-idealities. [ABSTRACT FROM AUTHOR]

This paper introduces a methodology able to produce an exact valid and physically meaningful circuit representation out of generic multi-port passive linear state-space models. The proposed method has a strong theoretical relevance as it allows the generation of equivalent netlists whose RLC values are guaranteed positive, without applying any additional approximations, and based only on coordinate transformations and circuit laws interpretation. In this sense it can be viewed as a generalization of Foster's synthesis that is guaranteed to produce a circuit description containing only elements with physical meaning. In addition, it also presents pratical advantages, as it generates a very sparse circuit, whose usage is highly efficient within standard simulation and analysis platforms. Furthermore, the synthesized circuit can be easily included in any standard environment for simulation, verification, delay calculation, symbolic analysis, etc., and in combination with other models for system-level detailed simulation, which further increases the practical relevance of the proposed approach. [ABSTRACT FROM AUTHOR]

Smart Power integrated circuits receive an increasing attraction recently, especially in automotive industry. Substrate noise coupling is one of the major causes of failure in this kind of integrated circuits that requires circuit redesign and increases the overall cost. An exhaustive failure analysis is needed to identify failures due to substrate coupling. In this paper, we present a post-layout extraction and simulation methodology for substrate parasitic modeling. Based on this methodology, we have developed a dedicated computer-aided-design tool that is used for substrate extraction from layout patterns. The extraction employs a meshing algorithm for substrate parasitic generation. To validate the substrate model, the process of benchmarking uses industrial design structures in $0.35\mu m$ high-voltage-CMOS technology. Two test cases in transient simulation are considered in this work. The first one is a common used current mirror circuit. Our tool predicts the interference of substrate currents to this basic circuit. The second test case is an industrial design test-chip where parasitic coupling is investigated in a standard automotive test. Eventually, by using the proposed CAD tool, it becomes possible to simulate the behaviors of substrate noise at early phase before fabrication. [ABSTRACT FROM PUBLISHER]

Designing a SPICE model is a critical step toward understanding the behavior of the resistive random access memory (RRAM) devices when integrated in memory design for the future generation storage devices. In this paper, a SPICE model is developed for the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM. The proposed model emphasizes the impact of the change in the switching layer thickness on the device behavior at low resistance state (LRS), high resistance state (HRS), and the transitional period. The validity of the proposed model is verified through using three different sets of experimental data from \textrmPt/Ta2\textrm{O}5/\textrm{TaO}x/\textrm{Pt} RRAM with switching layer thickness smaller than 5 nm. The SPICE model reproduced all the major features from the experimental results for the SET and RESET processes and also the asymmetric and the symmetric characteristics in HRS and LRS, respectively. The proposed SPICE model matches the measured experimental results with an average error of < 11% and a maximum error of < 70%. It also showed stable behavior for its HRS and LRS regions under different types of input signals. The model is parameterized in order to fit into \textrmTa2\textrm{O}5/\textrm{TaO}x RRAM devices with switching layer thickness smaller than 5 nm, thus, facilitating the model usage. The model can be included in the SPICE-compatible circuit simulation and is suitable for the exploration of the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM device performance at circuit level. [ABSTRACT FROM AUTHOR]

A large class of transcendental equations involving exponentials can be made explicit using the Lambert W function. In the last fifteen years, this powerful mathematical tool has been extensively used to find closed-form expressions for currents or voltages in circuits containing diodes. Until now almost all the studies about the W function in circuit analysis concern the Kirchhoff (K) domain, while only few works in the literature describe explicit models for diode circuits in the Wave Digital (WD) domain. However explicit models of NonLinear Elements (NLEs) in the WD domain are particularly desirable, especially in order to avoid the use of iterative algorithms. This paper explores the range of action of the W function in the WD domain; it describes a procedure to search for explicit wave mappings, for both one-port and multi-port NLEs containing diodes. WD models, describing an arbitrary number of different parallel and anti-parallel diodes, a transformerless ring modulator and some BJT amplifier configurations, are derived. In particular, an extended version of the BJT Ebers-Moll model, suitable for implementing feedback between terminals, is introduced. [ABSTRACT FROM PUBLISHER]

Specialized hardware accelerators beyond von-Neumann, that offer processing capability in where the data resides without moving it, become inevitable in data-centric computing. Emerging non-volatile memories, like Ferroelectric Field-Effect Transistor (FeFET), are able to build compact Logic-in-Memory (LiM). In this work, we investigate the probability of error (Perror) in FeFET-based XNOR LiM, demonstrating the new trade-off between the speed and reliability. Using our reliability model, we present how Binarized Neural Networks (BNNs) can be proactively trained in the presence of XNOR-induced errors towards obtaining robust BNNs at the design time. Furthermore, leveraging the trade-off between Perror and speed, we present a run-time adaptation technique, that selectively trades-off Perror and XNOR speed for every BNN layer. Our results demonstrate that when a small loss (e.g., 1%) in inference accuracy could be accepted, our design-time and run-time techniques provide error-resilient BNNs that exhibit 75% and 50% (FashionMNIST) and 38% and 24% (CIFAR10) XNOR speedups, respectively. [ABSTRACT FROM AUTHOR]

A model-based strategy for an efficient power supply control used in a wireless sensor network is presented. The strategy, based on Pulse-Skipping Modulation, regulates the current charging a battery, delivered by a photovoltaic source, resulting in an accurate current regulation and highly efficient power management. The strategy is implemented on a microcontroller unit and compensates for the microcontroller self-absorbed current. The modulation signal is generated through a full software interface, reducing the requirement for external components. Experimental validations, performed on a charger prototype by using a laboratory photovoltaic device simulator, proved that both regulation accuracy, regulation resolution and converter efficiency achieved are superior to the classic Pulse-Width Modulation. The approach results in a simple practical implementation, carries over the advantages of an up-to-date model for the photovoltaic device, and serves the auxiliary purpose of using the photovoltaic source as an instantaneous solar irradiance sensor. [ABSTRACT FROM AUTHOR]

This paper presents a novel analysis of nonlinear circuits useful for the computation of the reactive power from only terminal measurements. The method computes the reactive power of unknown circuits based on the physical understanding of Maxwell equations. The proposed method is able to identify instantaneous quantities (circuit parameters, powers, etc.) for two physical equivalent models: series and parallel circuits. The parallel equivalent model shows advantages for multi-subsystems. Several numerical examples are provided for validation of the proposed method and to illustrate step-by-step the calculation details. To be compatible with digital instrumentation, a time discrete formulation is used for all calculations. All examples are simulated in MATLAB and the EMTP (Electro-Magnetic Transients Program). [ABSTRACT FROM AUTHOR]

This paper presents an event-driven simulation methodology for injection-locked oscillators. The proposed method adopts a phase-domain macromodel based on a perturbation projection vector (PPV), which expresses the oscillator's phase response using a nonlinear, time-varying differential equation. By expressing the PPV using a piecewise polynomial function, the PPV model can be simulated in an event-driven fashion on a digital logic simulator like SystemVerilog. While this piecewise polynomial approximation introduces a trade-off between the simulation accuracy and speed, our results show that the simulation accuracy quickly reaches its optimal value as the piecewise interval number increases even with first-order polynomials. The experimental results with an LC oscillator, ring oscillator, and burst-mode CDR models operating with both periodic and aperiodic inputs demonstrate that the proposed models achieve speeds up to 2\sim 30\times that of transistor-level Spectre simulations with the same accuracy. [ABSTRACT FROM PUBLISHER]

This paper presents an approximate closed-form transfer function model for diverse differential interconnects. The proposed model is simple, intuitive, and can accurately describe various interconnects satisfying the validity conditions which theoretically bound the approximation error. The proposed model also provides a conceptual circuit representation by analogy with an equivalent circuit model of a single-ended interconnect. The model's accuracy is verified by comparing calculated through- and crosstalk-transfer functions against w-element SPICE simulation results for various LC-dominant and RC-dominant interconnects. Our analysis also empirically verifies that the approximation error is bounded by the validity parameters. In addition, the computation time is improved by about 157 times compared to that of the previous numerical computation method built-in SPICE simulator. With the proposed channel model, designers can easily understand and analyze the behaviors of various differential interconnects without complex analysis. [ABSTRACT FROM AUTHOR]

We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm2, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes. [ABSTRACT FROM AUTHOR]

Recently, an in-memory analog circuit based on crosspoint memristor arrays was reported, which enables solving linear regression problems in one step and can be used to train many other machine learning algorithms. To explore its potential for computing accelerator applications, it is of fundamental importance to improve the computing speed of the circuit, i.e., the circuit response towards correct outputs. In this work, we comprehensively studied the transfer function of this circuit, resulting in a quadratic eigenvalue problem that describes the distribution of poles. The minimal real part of non-zero eigenvalues defines the dominant pole, which in turn dominates the response time. Simulations for multiple linear regression solutions with different datasets evidence that, the computing time does not necessarily increase with problem size. The dominant pole is related to parameters in the circuit, including feedback conductance, and gain bandwidth products of operational amplifiers. By optimizing these parameters synergistically, the dominant pole shifts to higher frequencies and the computing speed is consequently optimized. Our results provide a guideline for design and optimization of in-memory machine learning accelerators with analog memristor arrays. Also, issues including power consumption, impact of noise and variation of sources and memristors are investigated to offer a comprehensive evaluation of the circuit performance. [ABSTRACT FROM AUTHOR]

We illustrate novel optimization techniques via simulations for Hopfield networks constructed from manufacturable three-terminal Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic circuit elements. We first present a computationally-light, memristor-based, highly accurate static compact model for the SONOS synapses used in our simulations. We then show how to exploit analog errors in programming resistances and current leakage, and the continuous tunability of the SONOS synapses to enable transient chaotic group dynamics, to accelerate the convergence of a Hopfield network. We project improvements in energy consumption and time to solution relative to existing CPUs and GPUs by at least 4 orders of magnitude, and also exceed the projected performance of two-terminal memristor-based crossbars in addition to a 100-fold increase in error-resilient array size (i.e. problem size). [ABSTRACT FROM AUTHOR]

We propose a framework to analyze mm-wave baluns directly from physical parameters by adding a dimension of Machine Learning (ML) to existing electromagnetic (EM) methods. From a generalized physical model of mm-wave baluns, we train physical-electrical Machine Learning models that both accurately and quickly compute the electrical parameters of mm-wave baluns from physical parameters, reducing the need for full-wave simulations and advancing several aspects of mm-wave designs. One of the advancements is a fully automated design process that accurately generates full EM designs of mm-wave baluns when given an electrical specification and a metal option. The automated technique only takes several seconds to complete, compared to hours-weeks of the current trial-and-error methods, and notably the approach can optimize mm-wave baluns directly for the lowest metal loss. Another advancement is the theoretical interpretation of several high-level and abstract questions concerning mm-wave designs, in which we quantify the optimum transistor sizes for the last stage of a class-AB differential power amplifier on an on-chip process and derive the rule of thumb describing the inverse relationship between the optimum device sizes and mm-wave frequencies. [ABSTRACT FROM AUTHOR]

This article presents a novel circuit modeling method for online training and testing process of the neuromorphic chip crossbar array based on the resistive random access memory (RRAM). A modified RRAM compact model is developed to realize the fast and accurate update of multiple conductance levels. Two training mechanisms with and without write-verify scheme are modeled and investigated for classifying MNIST handwritten digits and both achieve a good recognition accuracy of more than 96%. The parasitic model of the unit cell of interconnects is constructed by the domain decomposition method (DDM) and the partial equivalent element circuit (PEEC) method, which is suitable to build up a crossbar array of any size. The impact of parasitic effects of interconnects on the recognition accuracy with and without write-verify scheme is analyzed and compared. The weights trained with write-verify scheme show better robustness to parasitic noises but training with write-verify scheme spends a longer time processing the same amount of data. [ABSTRACT FROM AUTHOR]

Wave Digital Filters (WDFs) turn circuits into networks of input-output relationships that can be computed in an explicit fashion. This is done through a linear port-wise mapping of Kirchhoff variables into pairs of incident-reflected waves introducing one scalar free parameter per port, called reference port resistance. Parameters are then used to eliminate the implicit equations relating wave variables, referred to as delay-free-loops. Unfortunately, this methodology can only be applied under strong linearity and topological conditions. This manuscript presents an extension of the WDF formalism involving a novel “cross-port” vector definition of waves, whose reference resistance is a matrix of free parameters. This generalization greatly simplifies the WDF implementation of circuits with two-port elements, such as operational amplifiers. It allows us to derive wave-based descriptions of elements such as nullors, for which no scattering relation is available in the literature. Moreover, it enables a full adaptation of a wide class of two-port elements, thus avoiding the delay-free-loops that would otherwise form in traditional WDFs. This new formalism allows us to implement a wider range of circuits with two-port elements in a modular fashion, since the topology and the elements can be modeled independently. [ABSTRACT FROM AUTHOR]

An innovative full time-domain macromodeling technique for general, linear multiport systems is described. The methodology is defined in a digital wave framework and time-domain simulations are performed via an efficient method called Segment Fast Convolution (SFC). It is based on a piecewise-constant (PWC) model of the impulse response of scattering parameters, computed starting from a piecewise-linear fitting of their step response (PWLFIT). Such step response is directly available from time-domain reflectometer measurements (TDR/TDT) or equivalent simulations. The model-building phase is performed in a fast automated framework and an analytic formulation of computational efficiency of the SFC with respect to the standard time-domain convolution is given. Two application examples are used to verify the PWLFIT performance and to perform a comparison with macromodeling methods defined in the frequency-domain, such as Vector Fitting (VF). [ABSTRACT FROM AUTHOR]

We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype high input count analog neural network with digital learning system chip. Designed as continuous-time circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration, and measurement results from individual sub-circuits across multiple dies. The circuit dynamics matches with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing. [ABSTRACT FROM AUTHOR]

A static random access memory (SRAM) operational mismatch (SOMM) corner model and a methodology to efficiently estimate the SRAM read and write stability yield with the SOMM corner model are proposed. The proposed SOMM corner model effectively finds the combination of the transistor mismatch in SRAM, which represents the worst SRAM read or write operation in the given probabilistic distance (e.g., six sigma), and the SRAM yield can be estimated from the smallest probabilistic distance at which read or write operation failure occurs. With the proposed SOMM corner model implemented in the process design kit, the circuit designers can optimize the SRAM design by estimating the SRAM yield with significantly fewer computational resources, compared with the previous Monte Carlo-based methodologies. Numerical experiments show that the yield estimated by the proposed methodology matches well with the yield by Monte Carlo with importance sampling (error < 0.1 sigma); the simulation time takes less than 1 min, which is three orders of magnitude speedup over the conventional importance sampling methods. [ABSTRACT FROM PUBLISHER]

The ability of slime mould to learn and adapt to periodic changes in its environment inspired scientists to develop behavioral memristor-based circuit models of its memory organization. The computing abilities of slime mould Physarum polycephalum have been used in several applications, including to solve mazes. This work presents a circuit-level bio-inspired maze-solving approach via an electronic model of the oscillatory internal motion mechanism of slime mould, which emulates the local signal propagation and the expansion of its vascular network. Our implementation takes into account the inherent noise existent in the equivalent biological circuit, so that its behavior becomes closer to the non-deterministic behavior of the real organism. The efficiency and generality of the proposed electronic computing medium was validated through SPICE-level circuit simulations and compared with data from two cardinally different biological experiments, concerning 1) enhancing of Physarum's protoplasmic tubes along shortest path and 2) chemo-tactic growth by diffusing chemo-attractants. [ABSTRACT FROM AUTHOR]

We present a methodology to simulate industrial integer- $N$ phase-locked loops (PLLs) at a verification level, as accurate as and faster than transistor-level simulation. The accuracy is measured on the PLL factors of interest, i.e., locking time, power consumption, phase noise and jitter (period and long-term). The speedup factor tends to the division ratio $N$ for device-noise simulations. We develop a unifying technique which is able to deal with both noise-free and device-noise analyses, taking into account nonlinear and second-order effects visible at transistor-level simulation only, whereas previous works focused on one of the two analyses, separately. The procedure is based on oscillator’s sensitivity analysis and on the creation of a phase macromodel for the voltage-controlled oscillator (VCO) together with the loop divider (the phase model is called VCODIV), whilst the other PLL’s blocks remain at transistor level. The macromodel’s phase law is characterized by a piecewise linear curve, representing the sensitivity of the VCODIV output’s phase deviation with respect to the voltage variation of the VCO’s control pin, and by the effects of all the VCO’s and divider’s noise sources on the model’s output. We show two experiments on industrial PLLs, and provide guidelines for designers which highlight the steps needed to implement the methodology by using well-known analyses in circuit simulation and Verilog-A for the creation of the macromodel. [ABSTRACT FROM AUTHOR]

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation. [ABSTRACT FROM PUBLISHER]

The inverse of a recently proposed hysteresis and creep circuit model is proposed and discussed. The model is particularly suitable for piezoelectric actuators and its inverse can be used for open-loop compensation of the undesired nonlinearities in high-precision applications. The inverse model is defined, analyzed in terms of conditions ensuring a correct compensation, and discretized to provide a digital compensation algorithm suitable for implementation in low-cost programmable devices. Quantitative results on experimental data are provided and discussed, including the compensation on an atomic force microscope. [ABSTRACT FROM PUBLISHER]