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In this paper, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on the high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation) without needing a detailed electrical simulation. Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, MDM Laboratory. The parameters extraction procedure is also discussed. The obtained results clearly show that the model proposed in this paper is able to capture the influence of the programming pulse parameters (i.e. pulse duration and height) changes. This is accomplished by the introduction of a parameter, which is related to the specific device technology. [ABSTRACT FROM AUTHOR]

In this paper, we present an approach to nonlinear system approximation, called the lattice trajectory piecewise linear (LTPWL) model. The approach involves determining a lattice piecewise linear (PWL) approximation to the state trajectory of a nonlinear system. It has been shown in the literature that the lattice PWL expression can represent any PWL function in any dimension. After the LTPWL approximation has been obtained, the order of each model piece is reduced using a Krylov projection technique. Compared to existing trajectory piecewise linear (TPWL) models, which are quasi-PWL in the whole region, LTPWL models are virtually linear in each subregion. Besides, the single output LTPWL model can be seen as a special kind of TPWL model, in which only one weight is 1, and the other weights are 0. In general, for multiple output LTPWL model, the weights set to be 1 for each component are different, which makes the LTPWL model more flexible in approximation of nonlinear function. The proposed strategy is applied to simulate diode circuits, and the experimental results show that the performance of the LTPWL model is better than that of the traditional TPWL model in terms of approximation accuracy and generalization ability. [ABSTRACT FROM AUTHOR]

The simulation of the full netlist of a phase locked loop (PLL) is resource demanding due to the prohibitive time needed to derive output noise, spurs, and transient performance from detailed transistor-level simulations. To overcome this limitation, behavioral models are needed but they must be accurate and time-efficient. This paper introduces a new behavioral macro-model of the charge-pump PLL, addressing both spectral analysis and lock-in transient computation. To meet both accuracy and simulation efficiency, the model accounts for the time-variant transfer of noise and disturbances, and a novel procedure is introduced to extract the model parameters via transistor-level periodic steady-state simulations. To describe the nonlinear dynamics, the model also includes the voltage-controlled oscillator and charge-pump nonlinear characteristic computed via transistor-level simulations. The proposed macro-model has been tested on a 2.765-GHz PLL, and the results are compared against the noise transient simulation of the PLL full netlist. Phase noise and amplitude of spurious tones, both inherently generated and induced by external disturbances, are predicted within ±2 dB. Lock-in transients are also described with an accuracy within a few percent. On the other hand, the simulation time reduction is two/three orders of magnitude for both spectral analyses and transient simulations, depending on the PLL parameters. [ABSTRACT FROM PUBLISHER]

This paper introduces a methodology able to produce an exact valid and physically meaningful circuit representation out of generic multi-port passive linear state-space models. The proposed method has a strong theoretical relevance as it allows the generation of equivalent netlists whose RLC values are guaranteed positive, without applying any additional approximations, and based only on coordinate transformations and circuit laws interpretation. In this sense it can be viewed as a generalization of Foster's synthesis that is guaranteed to produce a circuit description containing only elements with physical meaning. In addition, it also presents pratical advantages, as it generates a very sparse circuit, whose usage is highly efficient within standard simulation and analysis platforms. Furthermore, the synthesized circuit can be easily included in any standard environment for simulation, verification, delay calculation, symbolic analysis, etc., and in combination with other models for system-level detailed simulation, which further increases the practical relevance of the proposed approach. [ABSTRACT FROM AUTHOR]

Designing a SPICE model is a critical step toward understanding the behavior of the resistive random access memory (RRAM) devices when integrated in memory design for the future generation storage devices. In this paper, a SPICE model is developed for the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM. The proposed model emphasizes the impact of the change in the switching layer thickness on the device behavior at low resistance state (LRS), high resistance state (HRS), and the transitional period. The validity of the proposed model is verified through using three different sets of experimental data from \textrmPt/Ta2\textrm{O}5/\textrm{TaO}x/\textrm{Pt} RRAM with switching layer thickness smaller than 5 nm. The SPICE model reproduced all the major features from the experimental results for the SET and RESET processes and also the asymmetric and the symmetric characteristics in HRS and LRS, respectively. The proposed SPICE model matches the measured experimental results with an average error of < 11% and a maximum error of < 70%. It also showed stable behavior for its HRS and LRS regions under different types of input signals. The model is parameterized in order to fit into \textrmTa2\textrm{O}5/\textrm{TaO}x RRAM devices with switching layer thickness smaller than 5 nm, thus, facilitating the model usage. The model can be included in the SPICE-compatible circuit simulation and is suitable for the exploration of the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM device performance at circuit level. [ABSTRACT FROM AUTHOR]

A large class of transcendental equations involving exponentials can be made explicit using the Lambert W function. In the last fifteen years, this powerful mathematical tool has been extensively used to find closed-form expressions for currents or voltages in circuits containing diodes. Until now almost all the studies about the W function in circuit analysis concern the Kirchhoff (K) domain, while only few works in the literature describe explicit models for diode circuits in the Wave Digital (WD) domain. However explicit models of NonLinear Elements (NLEs) in the WD domain are particularly desirable, especially in order to avoid the use of iterative algorithms. This paper explores the range of action of the W function in the WD domain; it describes a procedure to search for explicit wave mappings, for both one-port and multi-port NLEs containing diodes. WD models, describing an arbitrary number of different parallel and anti-parallel diodes, a transformerless ring modulator and some BJT amplifier configurations, are derived. In particular, an extended version of the BJT Ebers-Moll model, suitable for implementing feedback between terminals, is introduced. [ABSTRACT FROM PUBLISHER]

This paper presents an event-driven simulation methodology for injection-locked oscillators. The proposed method adopts a phase-domain macromodel based on a perturbation projection vector (PPV), which expresses the oscillator's phase response using a nonlinear, time-varying differential equation. By expressing the PPV using a piecewise polynomial function, the PPV model can be simulated in an event-driven fashion on a digital logic simulator like SystemVerilog. While this piecewise polynomial approximation introduces a trade-off between the simulation accuracy and speed, our results show that the simulation accuracy quickly reaches its optimal value as the piecewise interval number increases even with first-order polynomials. The experimental results with an LC oscillator, ring oscillator, and burst-mode CDR models operating with both periodic and aperiodic inputs demonstrate that the proposed models achieve speeds up to 2\sim 30\times that of transistor-level Spectre simulations with the same accuracy. [ABSTRACT FROM PUBLISHER]

We propose a framework to analyze mm-wave baluns directly from physical parameters by adding a dimension of Machine Learning (ML) to existing electromagnetic (EM) methods. From a generalized physical model of mm-wave baluns, we train physical-electrical Machine Learning models that both accurately and quickly compute the electrical parameters of mm-wave baluns from physical parameters, reducing the need for full-wave simulations and advancing several aspects of mm-wave designs. One of the advancements is a fully automated design process that accurately generates full EM designs of mm-wave baluns when given an electrical specification and a metal option. The automated technique only takes several seconds to complete, compared to hours-weeks of the current trial-and-error methods, and notably the approach can optimize mm-wave baluns directly for the lowest metal loss. Another advancement is the theoretical interpretation of several high-level and abstract questions concerning mm-wave designs, in which we quantify the optimum transistor sizes for the last stage of a class-AB differential power amplifier on an on-chip process and derive the rule of thumb describing the inverse relationship between the optimum device sizes and mm-wave frequencies. [ABSTRACT FROM AUTHOR]

We present a methodology to simulate industrial integer- $N$ phase-locked loops (PLLs) at a verification level, as accurate as and faster than transistor-level simulation. The accuracy is measured on the PLL factors of interest, i.e., locking time, power consumption, phase noise and jitter (period and long-term). The speedup factor tends to the division ratio $N$ for device-noise simulations. We develop a unifying technique which is able to deal with both noise-free and device-noise analyses, taking into account nonlinear and second-order effects visible at transistor-level simulation only, whereas previous works focused on one of the two analyses, separately. The procedure is based on oscillator’s sensitivity analysis and on the creation of a phase macromodel for the voltage-controlled oscillator (VCO) together with the loop divider (the phase model is called VCODIV), whilst the other PLL’s blocks remain at transistor level. The macromodel’s phase law is characterized by a piecewise linear curve, representing the sensitivity of the VCODIV output’s phase deviation with respect to the voltage variation of the VCO’s control pin, and by the effects of all the VCO’s and divider’s noise sources on the model’s output. We show two experiments on industrial PLLs, and provide guidelines for designers which highlight the steps needed to implement the methodology by using well-known analyses in circuit simulation and Verilog-A for the creation of the macromodel. [ABSTRACT FROM AUTHOR]

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation. [ABSTRACT FROM PUBLISHER]

The inverse of a recently proposed hysteresis and creep circuit model is proposed and discussed. The model is particularly suitable for piezoelectric actuators and its inverse can be used for open-loop compensation of the undesired nonlinearities in high-precision applications. The inverse model is defined, analyzed in terms of conditions ensuring a correct compensation, and discretized to provide a digital compensation algorithm suitable for implementation in low-cost programmable devices. Quantitative results on experimental data are provided and discussed, including the compensation on an atomic force microscope. [ABSTRACT FROM PUBLISHER]