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This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased $\Sigma \Delta $ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a $10\times $ enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of $\Sigma \Delta $ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply). [ABSTRACT FROM AUTHOR]

A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is $9\times $ improvement on the state-of-the-art. [ABSTRACT FROM AUTHOR]

Accurately resolving small fluorescence power variations in presence of noise and high-background tissue autofluorescence from deep brain structures with a fiber photometry system requires highly linear and sensitive photo detectors. This paper presents a high-dynamic range (DR) CMOS biosensor fusing a low-noise photosensing front-end with a high-precision extended counting analog-to-digital converter (ADC) with noise cancellation to detect florescence neural signal fluctuations of very low incident power. The 7 MSBs are resolved by a first order continuous-time resettable $\Sigma \Delta $ ADC, whereas the residue voltage is quantized by a 10-bit single slope ADC for enabling wide-dynamic range and high-precision fluorescence sensing. The reset noise is canceled out by an embedded noise cancellation scheme which is subtracting the reset noise from the signal using a correlated double sampling scheme. Unlike other solutions, the biosensor has a short conversion time of $306.5~\mu \text{s}$ compared to a typical fluoresence sampling period of 10 ms, providing a very low duty cyle of 3%, which is a key to achieve low excitation source power consumption in this application to extend system autonomy, and to avoid photobleaching and phototoxicity in the tissue. The proposed optoelectronic biosensor is implemented in a 0.18- $\mu \text{m}$ CMOS technology, consuming $93~\mu \text{W}$ from a 3.3-V supply voltage while achieving a DR of 104 dB, a minimum detectable current of $1.3~\text {pA}_{\mathrm{ rms}}$ , and a chip area of 0.475 mm2. We present the measured performance of the biosensor using an optical experimental setup including a LED driver, a fiber optic, and a test board. [ABSTRACT FROM AUTHOR]

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation are investigated. The digitally controlled shunt-capacitor inverter (SCI) delay cell leads to an extremely small design with the delay line being the only analog component, while the voltage controlled current-starved inverter (CSI) delay cell has a lower power consumption and less jitter. The proposed design procedure of the SCI based DLL allows fast simulation using Verilog based models since no analog low pass filter is required. Using the proposed modeling technique for the PDC, the behavior of the DLL can be estimated based on input clock jitter specifications. The SCI and CSI based multiphase DLL designs are fabricated in a 65nm CMOS process operated from a 1.2V supply. The proposed SCI based DLL occupies only 0.0048mm2 of active area and consumes 2.25mW at 2.5GHz input frequency with a 622.6MHz sample clock. The RMS jitter of the circuit is 1.2 ps and 1.4 ps for the DLL loop and the phase shifter loop, respectively. The RMS jitter is significantly reduced with the CSI based DLL to 0.86 ps and the power consumption of 2.64mW at 4GHz input frequency with a 996.1MHz sample clock provides an improved power efficiency compared to the SCI based DLL. As a trade-off, the area is increased to 0.0085mm2 due to the use of a $\Delta \Sigma $ modulator and an analog low pass filter. [ABSTRACT FROM AUTHOR]