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This paper presents a full hardware implementation of a magnetic tunnel junction based stochastic tunable bitstream generator. It provides highly accurate control of the switching probability, while showing important robustness to process and temperature variations. We propose a new architecture of sensing scheme based on the pre-charged sense amplifier approach that uses an asynchronous digital module to control the internal signals of the sense amplifier with the purpose of improving the reliability against the timing hazards and reducing the power consumption by detecting the end of the reading to stop the required static currents. The circuit also features a digital feedback loop that analyzes the output bitstream and adapt the current in such a way that the bitstream encodes precisely the required probability. This circuit features an important bit generation rate at a low energy cost. Based on an exhaustive characterization of the circuit, we provide a behavioral description in Verilog, with timing and power files to be integrated as a standard cell in the digital design flow for application level evaluation of the performance. Thus, we also provide a design and evaluation flow from device to digital level of abstraction. [ABSTRACT FROM AUTHOR]

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and $1080~\mu \text{W}$ output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique for single slope analog to digital converter (SSADC) to suppress the row-wise noise in CMOS image sensor. A sample switch is used in the current-steering DAC to reduce the noise introduced by bias circuits, which will deteriorate the characteristic of uniformity in the row direction. The sample switch can fix the voltage which biases the current source in the current-steering DAC when generating a ramp to avoid the ramp fluctuation in the time domain. The digital correlated double sampling is used to reduce the non-uniformity in column-level ADCs. The CMOS image sensor prototype is fabricated in 110nm 1P3M process. The 10-bit SSADC achieves DNL of −0.20 / +0.15 LSB and INL of −1.35 / +0.91 LSB at a sampling frequency of 29.2 KHz. It is proved that the row-wise noise is reduced from $764~\mu {\mathrm {V}}_{\text {rms}}$ to 163 $\mu {\mathrm {V}}_{\text {rms}}$ at a frame rate of 228 fps using the proposed sample switch structure. The prototype photos taken by the sensor show that the row-wise noise is reduced under the low-illumination circumstance effectively. [ABSTRACT FROM AUTHOR]

In this paper, a generic, low-noise, negative-voltage generator with wide tuning range and moderate driving capacity is presented. The highly integrated solution, incorporating a fully-integrated charge-pump and a regulator block, requires only one off-chip capacitor that can be shared with the supply decoupling capacitors. The fully integrated charge-pump operation is analyzed quantitatively, and a closed-form expression of its output impedance is derived. Powered from a single 3.3-V dc input, the output has a tuning range from −4.4 to +2.1 V for biasing applications, while the design supports a maximum load current of 250, 550, and $800~\mu \text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mVPP, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $\mu \text {V}_{\mathrm{ rms}}$ and the noise floor is under $5~\mu \text {V}_{\mathrm{ rms}}$. The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm2. [ABSTRACT FROM AUTHOR]

Miniaturized thin-film thermoelectric generators (TEGs) are emerging energy harvesting sources suitable for wearable and implantable applications. However, these sources usually exhibit large internal equivalent series resistance (ESR) that leads to low energy conversion efficiency and self-startup failures at ultra-low voltages. This paper presents a highly efficient boost converter with a novel Power-on-Reset (PoR) based self-startup circuit for systems harvesting the micro-scale thermal energy. The proposed circuit generates a train of pulses to kick start the self-startup through an internal feedback loop formed by the ESR of TEG, an auxiliary boost converter and a PoR circuit. The self-startup circuit is automatically disabled after the startup operation with a quiescent power consumption of 2 nW. A boost converter test chip with the proposed self-starter was fabricated in 65-nm CMOS technology node. It achieved a self-startup TEG voltage of 220 mV and a peak conversion efficiency of 76%. The minimum input voltage to sustain the boost operation is as low as 85 mV after the startup. [ABSTRACT FROM PUBLISHER]

High performance mixed signal (HPMS) platforms require stringent overall system and subsystem performance. The ability to design ultra-low power systems is used in a wide range of platforms including consumer, mobile, identification, healthcare products and microcontrollers. In this paper we present an overview of low power design techniques, challenges and opportunities faced in an industrial research environment. The paper presents strategies on the deployment of low power techniques that span from power-performance optimization scenarios accounting for active and standby operation modes to the development of multi-core architectures suitable for low voltage operation. [ABSTRACT FROM AUTHOR]

This paper introduces a discrete wheel-switching chaotic system (DWSCS). Changing the controlling sequence of the wheel switch allows DWSCS to generate a large number of new chaotic sequences from a set of existing chaotic maps (seed maps). Simulations and analysis demonstrate the DWSCS's characteristics and chaotic behaviors. An FPGA design of DWSCS shows its effectiveness in hardware implementation. We also propose a pseudo-random number generator using DWSCS whose excellent performance has been shown in experiments and comparisons. [ABSTRACT FROM AUTHOR]

Herein, we present a multi-energy harvesting interface integrated circuit (IC) that enables the efficient combination of heterogeneous power sources. An electromagnetic vibration energy generator (EVG) and a thermoelectric energy generator (TEG) are the two energy sources, which have quite different internal resistance (tens and kilo-Ohms). To solve the challenge of combining heterogeneous sources, we propose a current boost converter (CBC), which achieves the resistance transformation as well as the source type conversion. The challenge of realizing maximum power point tracking (MPPT) for each source is tackled by using a multi-task MPPT controller, which is efficiently shared between the two sources. To achieve energy harvesting under uncertain and random source conditions, we propose an input ($V_{\text {IN}}$)-dependent clock generator (VCG) and a vibration pulse detector (VPD). The VCG tracks the change of source conditions to generate the clock for the MPPT controller. The VPD allows tracking of the random amplitude and frequency changes of the EVG. The energy harvester is fabricated in a 0.18 $\mu \text{m}$ process with a thick top-metal option. Measured results show successful source detection, switching, and MPPT operation. The proposed IC provides an output power of up to 119 $\mu \text{W}$ with an end-to-end peak efficiency of 82% by consuming 582 nW. [ABSTRACT FROM AUTHOR]

Dedicated to neuron stimulation circuits, a stage-selective negative voltage generator is proposed to enhance the overall power efficiency. Since the supplied voltage of the stimulus driver is subject to applications and treatments, an extensive output requirement of supply is demanded to achieve energy-efficient stimulation. The charge pump is implemented as a negative voltage generator for on-chip design. In a limited area, excess power loss is eliminated by reconfiguring the cascaded architecture and clocks. Digitally programmable voltage levels can be outputted by varying the number of stages dynamically. The function of stage selection is achieved by the proposed stage-selective scheme. With appreciate control, the stage-selective negative voltage generator can maintain higher power efficiency under different output voltage levels and loading conditions. The technique improves 40% power conversion ratio at most but only leads to an increment of 8% in area occupation. The measured output voltage covers from −0.3 V to −9.3 V within a maximum 5.5-mA output current, which is verified in a 0.25- $\mu \text{m}$ BCD process. [ABSTRACT FROM AUTHOR]

We present a circuit technique to extract true random numbers from carrier capture and emission in oxide traps in the emerging redox-based resistive memory (ReRAM). This phenomenon that appears as small changes in current magnitude passing through the device is known as random telegraph noise (RTN) and is increasingly becoming a source of reliability issues in nanometer-scale devices. We demonstrate a circuit that exploits TRN suitable for a true random number generator (TRNG) in security applications, where the system is secure from different adversarial attacks, including side-channel monitoring and machine learning analysis. We experimentally characterize RTN in ReRAMs and extract its dependency to temperature, voltage, and area. We introduce an RTN harvesting circuit to mitigate sensitivities to temperature fluctuations, injected supply noise, and power signal monitoring. We reduced bias and imbalance in data due to high-speed sampling via von Neumann whitening. The circuit is compared to conventional non-differential readout approach. Our approach shows a 7.26 times improvement in autocorrelation and significant resilience against the injected supply noise. We also demonstrate the TRNG’s quality and robustness using statistical tests and machine learning attacks. The output of the generator satisfies statistical tests for randomness and is immune to modeling attacks based on the machine learning methods. [ABSTRACT FROM AUTHOR]

A precision bandgap reference has been developed in a 0.18~\mu \text m BiCMOS process that achieves ±3 ppm/°C temperature drift at ±3 $\sigma $ from −40 °C to 110 °C. The reference is designed to utilize single temperature trim and standard components. A 3.65 V switched capacitor reference voltage is provided to a $2^{{\textrm {nd}}} order delta-sigma modulator ADC to digitize a battery cell voltage. The switched capacitor reference utilizes fully differential sampling which reduces the errors from channel charge injection and clock feedthrough introduced by pseudo-differential sampling. A new technique for sampling a \text V{\textrm {be}} voltage directly onto the output of the reference’s differential amplifier has been developed that removes the error that would be introduced from differentially sampling the \text V{\textrm {be}} and the \Delta \text V{\textrm {be}} voltage terms independently. The bandgap reference and ADC combination have an input referred noise spectral density of 4.7~\mu \text V/\surd Hz from 0.1 to 162 Hz yielding 15 stable output bits. [ABSTRACT FROM AUTHOR]

An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 \mum CMOS process covers 6–10 bit resolution and 0.5 V–0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300\times 700~ \mum^2. [ABSTRACT FROM AUTHOR]

A new scheme of a gain/efficiency-improved serial- parallel switched-capacitor converter (SPSCC) is proposed by combining an adaptive-conversion-ratio (ACR) and pulse-width- modulation (PWM) control for step-up DC–DC conversion. For improving gain, the power part consists of one mc-stage cell and one nc-stage cell in cascade to obtain the step-up gain of (mc+1)\times(nc+1) at most. For improving efficiency, the ACR control with adapting stage number m,n is presented to select a proper gain of (m+1)\times(n+1) (m=1,2,\ldots,mc, n=1,2,\ldots,nc) according to the desired output. Further, the PWM control is adopted to enhance output regulation as well as robustness to source/loading variation. Some theoretical analysis and control design include: formulation, steady-state analysis, conversion ratio, efficiency, output ripple, stability, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a SPSCC prototype, and all results are illustrated to show the efficacy of this scheme. [ABSTRACT FROM PUBLISHER]

A triple-mode step-up/step-down switched-capacitor DC-DC converter is proposed, and it can work with a wide input voltage range. There are three operational modes in the proposed converter: triple-step-up, double-step-up, and step-down modes. A built-in clock generator was designed to generate a constant switching frequency, independent of the input voltage. The proposed circuit was implemented by a 0.35-\mum CMOS mixed-signal 2P4M 3.3/5 V polycide process with a die area of 1.56\times 1.47\ mm^2. The output voltage is fixed at 3.3 V, while the input voltage range is 1.8–5 V. The maximal load current for a 1.8-V input voltage is 10 mA, while it increases to 30 mA when the input voltage is larger than 3 V. [ABSTRACT FROM PUBLISHER]

An output voltage ripple aware design of different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is presented. A mathematical analysis has been carried out to model the output voltage ripple of random switching converter. Simulations of the converter have been undertaken and measured results from the converter fabricated with a standard 0.35 \mum CMOS process verify the proposed design approach. From experimental results, a carefully designed ramp can reduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance and capacitance comparing to the conventional design. [ABSTRACT FROM AUTHOR]