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The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is $0.291 \times 1.457\,\,\mu \text{m}^{2}$. The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements. [ABSTRACT FROM AUTHOR]

This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. The accuracy is demonstrated by comparing the results obtained using the proposed methodology with those obtained using transient electrical simulation results for three different SC circuits: a first order SC passive filter, a second order SC lowpass filter, and a second order SC bandpass filter, showing that the results are in good agreement with the more time consuming electrical simulation of the circuits. [ABSTRACT FROM PUBLISHER]

This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input. Novel DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 28 nm CMOS technology and are shown to have superior characteristics such as power and power-delay product (PDP) for a range of switching activities. Extensive Monte Carlo and voltage scaling simulations are performed to show that the presented designs are robust under PVT variations. [ABSTRACT FROM PUBLISHER]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2. [ABSTRACT FROM AUTHOR]

The design and analytical modeling of a high efficiency energy harvester comprising a passive voltage-boosting network (VBN) and a switching charge pump rectifier (CPR) is presented in this paper. To improve the power conversion efficiency (PCE), the VBN increases the voltage at the input of the CPR and provides control signals for switching. Unlike traditional Schottky and diode-connected MOS transistor rectifiers, the proposed orthogonally switching CPR (OS-CPR) comprises MOS transistors as voltage-controlled switches. Analytical models for the OS-CPR are developed and presented. Circuit-level optimization techniques are employed to reduce conduction and switching losses. Simulated in a 90 nm standard CMOS technology (IBM 9RF), a 5-stage 915 MHz OS-CPR achieves a dc voltage of 1.35 V and a PCE of 11.9% with a 1 M\Omega load at -18.2 dBm available input power (PS,AV). To show technology scalability of the design, the OS-CPR is also validated using AMS 0.18 \mum high-voltage (HV) CMOS technology. When benchmarked with traditional rectifiers, the OS-CPR (under similar conditions) achieves a higher PCE and a higher output dc voltage. The OS-CPR is easily scalable to operate over multiple sub-GHz ISM frequency bands. [ABSTRACT FROM PUBLISHER]

This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design strategy is proposed that introduces a switch-driver power consumption aware analysis of the switched current cell. The analysis of the major distortion mechanisms in the switched current cell allows the derivation of a design strategy for maximum linearity. This strategy is extended to include the power consumption of the switch drivers in function of the switched current cell design. To minimize the digital power consumption, low-power implementations of the thermometer decoder and switch driver circuits are introduced. [ABSTRACT FROM PUBLISHER]

In this work, we present an asynchronous MTJ-CMOS hybrid system with extremely fine-grained voltage scaling (EFGVS) technique. The supply voltage of the system is turned on/off by asynchronous bundled-data handshake signals. The MTJ write circuit is variation robust, self-terminated and redundant-write preventing. Besides, EFGVS and asynchronous data driven handshake enhance the timing robustness by removing the matching delay elements and reducing timing assumptions. The completion detection circuitry is also simplified. A RISC processor with proposed techniques is designed and fabricated by 55nm technology. The voltage supplies are turned on/off within tens of picoseconds. The energy for writing MTJs is 0.45pJ. The tolerance of the minimum TMR due to process variation is 75%. Sleep mode leakage power can be reduced over 10 $\times$ by powering off modules with the Break-even Time of 23.6 ns. Because of the extremely fine-grained voltage scaling, no more than 20% of the modules are powered on during the execution. [ABSTRACT FROM AUTHOR]

In order to combat the exponentially growing leakage power in modern microprocessors, researchers have proposed the use of alternative power-gating structures that can yield higher leakage savings with a much lower performance impact. A prime contender is an emerging CMOS-compatible power-gating device, the nanoelectromechanical systems (NEMS) switch. Compared to transistors, NEMS switches have zero off-state leakage, so for very long periods of sleep, their effectiveness is unparalleled. For systems with periods of faster on/off rates, however, their slower switching speed, high activation energy, and finite device lifetime become drawbacks. This motivates an exploration to determine whether NEMS switches are capable of fast, fine-grained power-gating. In this article, we provide an accurate energy model of functional-unit power-gating that allows us to effectively compare transistors and NEMS switches. It is also fast enough to support the optimization of a wide variety of circuit- and system-level parameters, including supply voltage, threshold voltage, and power-gating scheduler aggressiveness. Using this framework, we show that NEMS switch power-gates along with an ideal oracle power-gating policy can achieve an average 29.5% drop in total functional unit energy, compared to only 23.5% with transistor power-gates. A more realistic hardware-based policy for NEMS switches yields a 28.9% drop, compared to a 23.0% drop with transistors. [ABSTRACT FROM AUTHOR]