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This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

Field-Coupled Nanocomputing technologies have great potential to surpass CMOS technology because of their lower power consumption and higher device concentration. To ease the burden of placement and routing (P&R) problems for FCN circuits, many delicate two-dimensional clocking schemes have been proposed, upon which algorithms can solve the P&R problems more strategically. In this paper, we propose a two-level optimization strategy by using a genetic algorithm (GA) combined with an enhanced A* algorithm. Some circuit design requirements, such as clock synchronization, layout area, etc., are cleverly designed in the fitness value function of the GA. Numerical results demonstrate the effectiveness of the hybrid algorithm. In particular, compared to current tools, such as fiction and Ropper, the proposed algorithm can achieve an optimal solution with a higher success rate and a sizeable applicable circuit scale. In addition, the concept of design rule checking (DRC) was proposed in FCN and integrated into the algorithm, making the P&R results mapping from gate-level to cell-level more smoothly. Besides, the number of cross wires is significantly reduced, and the distribution of IO ports can be more effectively controlled. [ABSTRACT FROM AUTHOR]

In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, we propose a 5.28-mm $^{2}~4096$ -neuron 1M-synapse energy-efficient digital SNN hardware that can achieve ultra-low energy per synaptic operation of 4.5 pJ. The proposed neuron computing unit is implemented in pipeline architecture to achieve high synaptic processing speed. The proposed spike processing unit can significantly increase the processing speed of the neuron core by $1.9\times $ and $9.4\times $ when the spike injection rate is 50% and 10%, respectively. Besides, the increase in the processing speed of the neuron core leads to a reduction in energy consumption of up to 81.5%. An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper. This paper proposes a supervised STDP+ algorithm for SNN training, and the classification accuracy of the MNIST digits is 89.6% with 73.6% weight sparsity of the output layer. [ABSTRACT FROM AUTHOR]

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm2. The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported. [ABSTRACT FROM AUTHOR]

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. [ABSTRACT FROM AUTHOR]

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology. [ABSTRACT FROM AUTHOR]

Injection-locked ring oscillators (ILROs) are widely used for quadrature clock generators (QCG) in multi-lane wireline or optical transceivers because of their low power, low area, and technology scalability. However, locking a four-stage I/Q oscillator with a two-phase injection signal generates imbalances in amplitude and phase, resulting in I/Q phase errors and degraded jitter performance. This paper proposes a modified frequency-domain analysis with amplitude constraint for even-phase ILROs. Combining theoretical derivations with simulation results in 28nm CMOS technology, the behaviors of ring oscillators with partial injection and ILRO-based QCG are discussed and concluded. [ABSTRACT FROM AUTHOR]

The divider is one of the most complex hardware units in Stochastic Computing (SC); even though several new designs have been presented to reduce the computation latency of the conventional divider, all of them still require a considerable number of clock cycles. Moreover, they incur in low performance due to the employed arithmetic computational scheme. In this paper, a Delta Sigma Modulator (DSM) based stochastic divider is proposed. As an entirely digital circuit, the proposed divider offers the best computation latency and accuracy over all existing stochastic dividers found in the technical literature (with a typical reduction between 66.8% and 96.9% in the number of clock cycles and a reduction from $10^{\mathrm {-3.4}}$ to $10^{\mathrm {-3.9}}$ in the average mean square error for a 10-bit resolution). An SC-based Neural Network (NN) is considered as an initial case study to evaluate the advantages of the proposed design in an emerging application; results show that the proposed divider enables an SC-based NN to achieve a higher classification accuracy and hardware efficiency than existing designs. To show the flexibility of the proposed divider design, its application to Sobol-based sequences is also presented; also in this case, its superiority over other designs is confirmed. These features make the proposed design very attractive for hardware-constrained platforms; moreover, such a novel design approach that incorporates ideas from analog/mixed signal circuit design into a digital circuit design, can motivate other researchers to design efficient SC designs using similar schemes. [ABSTRACT FROM AUTHOR]

Computing systems working in harsh environment is prone to suffer from radiation-induced soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are the major reliability issue for circuits fabricated with nanoscale technology nodes. In this paper, we proposed a low-cost SET and SEU error tolerant flip-flop (SETU-TOFF). Based on the traditional flip-flop, two high-level sensitive redundant latches are added to latch the input data at different times, and a voter is designed for the correct output. It removes the timing overhead of temporal redundancy from the critical path of the systems. Comparing with the existing designs presented in literatures, SETU-TOFF has comprehensive fault tolerant capability with lower overheads; moreover, it doesn’t increase significant latency of the flip-flops. We use the SETU-TOFF cells to protect a pipeline of an OpenRISC microprocessor. Fault injection simulations show that SETU-TOFF can achieve 100% protection for the pipeline with negligible performance loss; additionally, it can detect and correct errors in real time without extra system control logic and clocks for errors recovery. [ABSTRACT FROM AUTHOR]

The analysis of injection-locked clock multipliers (ILCMs) using bang-bang phase detectors (BBPDs) is challenging due to the nonlinear BBPD and the multi-rate injected oscillator. This paper presents an explicit analysis of digital ILCMs using BBPDs and proposed an intuitive approach to optimizing parameters with given noise sources. A time-domain analysis in the single-clock domain is presented to solve the closed-form expression of jitter in the ILCM. The proposed approach exhibits good consistency with simulations, for various design parameters and noise cases. With the predicted input-referred jitter, the equivalent BBPD gain is resolved to derive the frequency-domain noise transfer functions in concise forms. To achieve the desired performance with given specifications, recommended design procedures are summarized based on the proposed analysis and verified by simulations. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme. [ABSTRACT FROM AUTHOR]

A random sampling-and-averaging (RSA) technique based on stochastic Monte Carlo methods is described in this paper for enhancing the accuracy of single-photon arrival-time measurements down to sub-picosecond ranges in emerging quantum applications. The theoretical variances of both synchronous and asynchronous RSA techniques are presented in the mathematical formats and experimentally verified by the Monte Carlo simulations. Meanwhile, the methodology of converting the mathematical models into an almost all-digital low-power integrated-circuit is elaborated by a circuit-level example with the instruction of setting circuit parameters. Along with the superior measurement resolution, scalable dynamic ranges, high linearity, high noise immunity, and low power/area consumption, the primary limitation of the RSA techniques has also been addressed for the forthcoming conversion-rate enhancement techniques. [ABSTRACT FROM AUTHOR]

In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to improve settling speed, and 1-bit redundancy is designed for calibration and dither injection. The TD-ADC with selective time domain quantization is implemented by a constant-current voltage to time converter (VTC) array and a direct positive feedback time domain comparator. The proposed VTC array can maintain high linearity with a large input swing in high-speed application. The prototype ADC was fabricated in a 28-nm CMOS process and occupied a core area of 0.074 mm2. Under a 0.95-V power supply, the chip achieves a measured peak SNDR of 53.2 dB and SFDR of 61.7 dB respectively at conversion rate up to 2.5 GS/s. The FOM is 48.2 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate $< 1\text{E}$ -10 with a power efficiency of 4.75 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

Millimeter-wave (mmWave) RF and analog front-end circuits are very susceptible to chip process and temperature variation, which cause I/Q mismatch and DC offset. As a consequence, the system performance can be seriously degraded, especially in wideband multi-Gb/s systems. This paper proposes an online estimation and compensation in the baseband receiver end of a single carrier (SC) system for TX and RX frequency independent (FI) initial and time-varying (TV) I/Q mismatch and DC-offset. Based on specification of IEEE 802.11ay, the compensated image rejection ratio (IRR) performance of the TX and RX FI I/Q mismatch effects can be improved from 16.43 dB to 54.70 dB at SNR of 25.52 dB. Moreover, we propose a novel algorithm based on the Golay sequence for estimation and compensation to cancel TX and RX initial/TV DC-offset. The DC-offset in the I/Q channel is improved from −56.46 dB/−58.56 dB to −97.30 dB/−98.70 dB at SNR of 25.52 dB. In the hardware implementation, a four-time parallelism architecture are proposed to work at a 625 MHz clock rate with a 28-nm HPC_PLUS CMOS process under 64-QAM mode for 15 Gbps transmission. Using a clock gating control scheme for FI I/Q mismatch and DC-offset estimator, the total power of the proposed the module can be reduced from 59.5 mW to 32.7 mW. The gate count and power of the proposed estimation/compensation design are only 2.94% and 1.69% of the overall digital RX baseband gate count and power consumption. [ABSTRACT FROM AUTHOR]

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit. [ABSTRACT FROM AUTHOR]

Generalized integrated interleaved (GII) codes nest a set of linear block codewords to generate codewords belonging to stronger codes. They are among the best error-correcting codes for next-generation hyper-speed digital communications and storage. Serial encoders for GII codes based on BCH codes have been previous investigated. They consist of BCH encoders whose inputs and outputs are multiplied by vectors decided by the nesting scheme. However, parallel GII encoders for high-speed systems cannot be designed by directly extending serial encoders due to the unique feature that BCH codes of different error-correcting capabilities are involved. Moreover, GII decoder complexity and latency can be greatly reduced by sharing the encoder to compute short remainders for syndrome computation. Although previous resource-shareable BCH encoders can be utilized to implement resource-shareable GII encoders, they are all serial. This paper first proposes a low-complexity scheme to handle the different error-correcting capabilities of the involved codes and align the input and parity symbols for parallel processing. Then two efficient parallel resource-shareable BCH encoder architectures to be used as GII encoder components are developed. The first design is achieved by deriving parallel register state update formulas for concatenated linear-feedback shift registers (LFSRs). Through reformulating the remainder polynomial divisions, the second design allows the inputs to be added to different LFSR taps, and accordingly reduces the complexity by a significant portion. For an example 160-parallel GII-BCH encoder considered for Flash memory applications, the second proposed design requires 14% smaller area compared to the first one. Besides both of them lead to around 50% latency reduction in the nested syndrome computation with small area overheads compared to the best possible alternative design. [ABSTRACT FROM AUTHOR]

In this paper, we present a new fast Fourier transform (FFT) hardware architecture called constant multiplier (CM) FFT. Whereas rotators in previous architectures must rotate among several different angles, the CM FFT exploits the use of constant multipliers to calculate the rotations. The paper explores the 4-parallel and 8-parallel radix-2 CM FFT, which calculates the FFT entirely by using constant multipliers. Later, radices $2^{k}$ are presented, with emphasis in radix-24 and radix-25 as the best alternatives. Experimental results for a 1024-point radix-25 CM FFT show that the proposed approach reduces the number of block random-access memories (BRAM) and digital signal processing (DSP) slices with respect to previous approaches, while achieving the highest clock frequency for a 4-parallel FFT architecture on field-programmable gate arrays (FPGAs) reported so far. [ABSTRACT FROM AUTHOR]

The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm2, whereas power consumption is 48.5mW in double output mode and 34mW in single output mode. [ABSTRACT FROM AUTHOR]

Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ($32.4\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$) to ($62.5\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$), depending on the variant. [ABSTRACT FROM AUTHOR]

Due to the low complexity in arithmetic unit design, stochastic computing (SC) has attracted considerable interest to implement Artificial Neural Networks (ANNs) for resources-limited applications, because ANNs must usually perform a large number of arithmetic operations. To attain a high computation accuracy in an SC-based ANN, extended stochastic logic is utilized together with standard SC units and thus, a stochastic divider is required to perform the conversion between these logic representations. However, the conventional divider incurs in a large computation latency, so limits an SC implementation for ANNs used in applications needing high performance. Therefore, there is a need to design fast stochastic dividers for SC-based ANNs. Recent works (e.g., a binary searching and triple modular redundancy (BS-TMR) based stochastic divider) are targeting a reduction in computation latency, while keeping the same accuracy compared with the traditional design. However, this divider still requires $N$ iterations to deal with $2^{N}$ -bit stochastic sequences, and thus the latency increases in proportion to the sequence length. In this paper, a decimal searching and TMR (DS-TMR) based stochastic divider is initially proposed to further reduce the computation latency; it only requires two iterations to calculate the quotient, so regardless of the sequence length. Moreover, a trade-off design between accuracy and hardware is also presented. An SC-based Multi-Layer Perceptron (MLP) is then considered to show the effectiveness of the proposed dividers over current designs. Results show that when utilizing the proposed dividers, the MLP achieves the lowest computation latency while keeping the same classification accuracy; although incurring in an area increase, the overhead due to the proposed dividers is low over the entire MLP. When using as combined metric for both hardware design and computation complexity the product of the implementation area, latency, power and number of clock cycles, the proposed designs are also shown to be superior to the SC-based MLPs (at the same level of accuracy) employing other dividers found in the technical literature as well as the commonly used 32-bit floating point implementation. [ABSTRACT FROM AUTHOR]

Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm2 and a power dissipation of 0.85W. [ABSTRACT FROM AUTHOR]

This paper describes a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture that does not use a charge pump (CP) or a linear time-to-digital converter (TDC). A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection under a low supply voltage. The CP-less analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. Unlike the TDC, the flip-flop PD has negligible contribution to the in-band phase noise over different supply voltages. To mitigate ΔΣ quantization noise and PD nonlinearity effects, an FIR-filtered ΔΣ modulation is employed for fractional division. The proposed fractional-N HPLL implemented in 65-nm CMOS operates with a 0.65-V supply except a 0.9-V digital/voltage-controlled oscillator (D/VCO), consuming 1.85 mW at 1.2 GHz. The phase noise of –97 dBc/Hz at 1-MHz offset frequency and the reference spur of –76 dBc with the programmable notch filter are achieved. The measured in-band fractional spur levels vary from –37 dBc to –58 dBc. The experimental results show that the proposed architecture is promising for low-voltage clock generation and modulation systems. [ABSTRACT FROM AUTHOR]

This paper presents a digital readout integrated circuit (DROIC) for small pitch medium-wave infrared (MWIR) starring focal plane arrays (FPAs). To overcome the limited in-pixel resolution of such DROICs, the concept of error shaping is introduced in pulse frequency modulation (PFM)-based pixels. Multiple integration operations are performed in a single frame and the residue charge from each integration phase is retained and injected into the next charge packet. This over-integration routine provides a high pass noise transfer function (NTF) equivalent to what is obtained in a first order sigma delta modulator. The concise structure of a PFM analog-to-digital converter (ADC) lends itself well to such an operation inside the pixel, while consuming low power. Along with a theoretical analysis of the technique, a prototype based on a $16\times 16$ array and sinc decimation filters is developed to demonstrate the performance of the proposed DROIC. With an in-pixel resolution of 5 bits and over-integration ratio (OIR) of 128, 395 noise electrons are demonstrated at full-well fill from the test array fabricated in a 90 nm bulk-CMOS process. [ABSTRACT FROM AUTHOR]

Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of −63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of −241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO’s phase noise (PN), leading to an in-band PN of −116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2. [ABSTRACT FROM AUTHOR]

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514 S/s prototype (ReDAC1) and on a 11-bit, 10.5 kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68 LSB (1.53 LSB) maximum INL, 1.54 LSB (1.0 LSB) maximum DNL, 76.4 dB (67.9 dB) THD, 79.7 dB (71.4 dB) SFDR and 71.3 dB (63.3 dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB). [ABSTRACT FROM AUTHOR]

Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106 years. [ABSTRACT FROM AUTHOR]

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself. [ABSTRACT FROM AUTHOR]

This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps. [ABSTRACT FROM AUTHOR]

This paper presents a time-division-multiplexed (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between multiple output channels. Clocked-analog operation is introduced to create idle periods that enable the shared controller to independently regulate different output channels through time-division multiplexing. Furthermore, an asynchronous transient enhancing technique is presented. Thanks to the controller sharing, the TDM CLDO is more area-efficient than conventional designs for supplying multiple outputs, especially when power stages and on-chip loads are small. To verify the effectiveness of the TDM CLDO, a dual-channel version is fabricated in a 130 nm CMOS process. Measurement results show that it can independently track two 100 kHz $0.3~\rm V_{pp}$ sinusoidal signals with 4 mV average output error at $100~\Omega $ load and 6 MHz clock frequency. For load transient responses, it can independently regulate two output channels to 1.05 V and 0.95 V with 41 mV/88 mV and 67 mV/39 mV overshoot/undershoot when both channels experience 5 mA current steps at $1.2~\rm V_{dd}$. To the best of our knowledge, this is the first time that hardware sharing is implemented for continuous closed-loop systems. [ABSTRACT FROM AUTHOR]

State-of-the-art approaches that perform root computations based on the COordinate Rotation Digital Computer (CORDIC) algorithm suffer from high latency in performing multiple iterations. Therefore, root computations based on the CORDIC algorithm cannot meet the strict latency requirements of some applications. In this paper, we propose a methodology for performing ${N}$ th root computations on floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed method divides an ${N}$ th root computation into several subtasks approximated by the PWL algorithm. It determines the widest segments of the subtasks and the smallest fractional width needed to satisfy the predefined maximum relative error $Max\_{}Err_{r}$. Our design is coded in Verilog HDL and synthesized under TSMC 40 nm CMOS technology. The synthesized results show that our design can reach the highest frequency of 2.703 GHz with an area consumption of $2608.84~\mu ~\text{m}^{2}$ and a power consumption of 2.4476 mW. Compared with one state-of-the-art architecture, our design saves 91.60%, 89.84%, and 63.33% of the area, power, and latency @1.89GHz frequency, respectively, while reducing $Max\_{}Err_{r}$ by 57.30%. In addition, it saves 94.52%, 92.68%, and 73.17% of the area, power, and delay @1.89GHz frequency, respectively, and reduces $Max\_{}Err_{r}$ by 1.65% when compared with the other state-of-the-art design. [ABSTRACT FROM AUTHOR]

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology. [ABSTRACT FROM AUTHOR]

This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is < 0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UIpp jitter tolerance up to 10 MHz for all the three modes. [ABSTRACT FROM AUTHOR]

In this paper, we study networks of coupled oscillators applied to the distributed synthesis of clock signals for large systems-on-chip. The oscillators are implemented as interconnected all-digital phase-locked loops (ADPLLs), which are asynchronous control systems. We address the issue of modelling, synchronization and stability of both a single ADPLL and interconnected ADPLLs. We prove that the stability domain is universal for large Cartesian networks, and it related to the domain for a single ADPLL. We show that within the stability domain the network synchronises to the reference signal both in frequency and phase. A hardware verification of Cartesian networks is presented, and it is consistent with our theoretical findings. The proposed design may be useful for multiples engineering and physics applications, including clock generation, distributed computations, beamforming, and other applications, where the control over time synchronicity is crucially important for the system performance. [ABSTRACT FROM AUTHOR]

Generalized integrated interleaved (GII) codes nest Reed-Solomon (RS) or BCH sub-codewords to generate codewords belonging to stronger RS or BCH codes. Their hyper-speed decoding and good error-correction capability make them one of the best candidates for next-generation terabit/s digital storage and communications. The key equation solver (KES) in the nested decoding stage causes clock frequency bottleneck and takes a large portion of the GII decoder area. Recent architectures reduce the critical path to two multipliers and rely on the application of the slow-down technique to further reduce it to one. The slow-down technique requires two sub-codewords to be interleaved in the nested KES. However, most of the time, the nested decoding only needs to be carried out on one sub-codeword and half of the clock cycles are wasted. This paper proposes two fast nested KES algorithms, both of which have one multiplier in the critical path without applying slow-down and accordingly reduce the latency of the nested KES to almost a half. The short critical path is achieved by algorithmic reformulations that enable the pre-computation of the scalars in parallel with polynomial updating. Our second design adopts scaled versions of the polynomials to enable product term sharing so that the number of multipliers in each pair of processing elements is reduced from 8 as in the first design to 4. Novel scaling and combined scalar computations are developed to keep the critical path one multiplier. For an example GII code over $GF(2^{8})$ that has 3 nested codewords, our designs achieve 49.9% reduction on the number of clock cycles needed in the nested KES compared to prior designs. Besides, our second design requires 22% less area than the first one under the same timing constraint. [ABSTRACT FROM AUTHOR]

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and $1080~\mu \text{W}$ output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV. [ABSTRACT FROM AUTHOR]

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template pulse, the noise effect of the receiver chain, and the template signal level. The proposed estimation procedure is validated by comparing its results with transient noise simulations. It is shown that increasing the template signal range in the correlator and improving the linearity of the phase interpolation transfer curve, at a given power consumption, enhances the receiver sensitivity by 2 and 3.5 dB, respectively. The BER estimation results also reveal that the effect of the template signal jitter on the sensitivity of the correlation-based IR receivers becomes dominant with the increasing input signal level. [ABSTRACT FROM AUTHOR]

This paper presents a compact impulse-radio ultra-wide band non-coherent receiver architecture for high data rate wireless neural recordings from active high-density CMOS-probes. The system is capable of receiving, synchronizing, and demodulating a continuous on–off keying pulse stream at 1 Gb/s and 4 GHz center frequency using an active area of 0.34 mm2 and a single 31.25 MHz crystal reference. An asynchronous threshold energy detector, including a pulse enhancement baseband with an all-digital back-end, recovers incoming transmitter clock (CDR) and acquires packet synchronization based on a data-aided mechanism (DPR). Results shows that a prototype of the receiver integrated in a 130 nm CMOS process recovers synchronization in 30 ns. The system includes I/O output buffers and driver logic at 1.8 V supply operating at 1 GHz on a 50 $\Omega $ load and crystal oscillator. Overall, it consumes 115 pJ/pulse, while the receiver core only consumes 12 pJ/pulse. This paper presents the receiver architecture, and experimental results show a sensitivity of −38 dBm at 10−3 packet error ratio. [ABSTRACT FROM AUTHOR]

This paper proposes a configurable direct digital frequency synthesizer (DDFS) based on the lookup-table (LUT)- rotation architecture. To break through the limitation of the single mode, the proposed DDFS is the first attempt which supports four-mode switching on chip. Taking the advantages of small LUT size and pipelined rotation, the DDFS achieves both high-speed and high-resolution properties. The multi-bit rotation tree is helpful to reduce the latency and register usage, which improves the agility and energy efficiency of the DDFS. A partition problem is raised in this paper, and we estimate the optimal solution through both the theory and experiment. Based on the partition, an output can achieve the highest spurious-free dynamic range (SFDR) with as small as possible LUT size. The functionality of the proposed DDFS has been validated in a Xilinx ZedBoard field-programmable gate array. The synthesis and layout results show that the chip achieves maximum 102-dBc SFDR and 2.2-GHz clock frequency. The power consumption and latency cycles reach minimum 6.9 mW/GHz and 7 cycles, which are 20% and 30% reduction compared with the state-of-the-art DDFS. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma–delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based $\Sigma \Delta $ modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation. [ABSTRACT FROM AUTHOR]

Manufacturing process variations and transistor’s aging effects are two major concerns for reliable design of nano-scale digital circuits. Correct functionality of flip-flops (FFs), as one of the most important elements in digital circuits, plays a key role in reliability of modern circuit designs. In this paper, a timing reliability improvement technique is proposed for master-slave FFs considering the impacts of process variations and aging effects. In this technique, the internal circuitry of the FF is restructured in order to improve the reliability by reducing the stress time (i.e. the time of being ON) of the transistors which are stacked in the feedback loop. Using Monte-Carlo based HSPICE simulations, the efficacy of the restructuring-based reliability improvement technique is shown considering various experimental conditions (i.e. different process variation ratios and lifetime values). The experimental results show that, the lifetime reliability of Master-Slave FFs improved by 22% in expense of 3% area overhead, 8% propagation delay absolute change, and 6% absolute power change in the presence of 20% variation ratio and 9 years of operation time. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is reduced by a factor of ${n}$. As a proof of concept, a 0.1-5 GHz RF filter with 75 dB and 82 dB harmonic rejection at 3rd and 5th order harmonics respectively is analyzed and simulated using MATLAB and Cadence Spectre-RF. Post-layout simulations are performed using CMOS 180 nm technology with 1.8 V supply voltage. The total power consumption of the chip is less than 8.5 mW while occupying a silicon area of 0.2 mm2. Furthermore, Noise Figure (NF) of the circuit is shown to be between 3.5 and 4.7 dB and its out-of-band IIP3 is +6 dBm. [ABSTRACT FROM AUTHOR]

In many applications such as gravimetric sensing, there is a need to rapidly estimate the center resonant frequency of the sensor system. This paper proposes and compares different quantized analog compressive sensing approaches for rapid frequency estimation. In particular, we discuss (a) Atomic norm Soft Thresholding - Semidefinite Programming (AST-SDP), (b) Atomic norm Soft Thresholding - Alternating Direction Method of Multipliers (AST-ADMM) and (c) Superfast Line Spectral Estimation (LSE) algorithms. As a result of this comparison we report that Superfast LSE achieves a good trade-off between computational speed, quantization, and error in frequency estimation among the three approaches. We further compare the compressive sensing approaches to several classical methods such as the Prony’s algorithm and the Pisarenko’s algorithm and show that compressive sensing based approaches remain robust to higher quantization errors. Finally, experimental results are shown for a quartz crystal and a MEMS based gravimetric sensor. Frequency measurement results with the quartz crystal show that a resolution of 0.1 ppm RMSE is achieved with the compressed sensing approach. [ABSTRACT FROM AUTHOR]

Generalized integrated interleaved (GII) codes nest linear block codewords to generate codewords belonging to stronger linear block codes. They can achieve very high throughput with excellent error-correcting capability. GII codes can be based on either Reed-Solomon (RS) or BCH codes. GII-BCH codes are the most promising candidate for error correction in next-generation terabit/s Flash and storage class memories, and optical communications. On the other hand, GII decoder implementation faces many challenges. In particular, the key equation solver (KES) in the nested decoding process causes not only clock frequency bottleneck but also large area. Although techniques have been developed recently to address these issues for GII-RS codes, they cannot be directly extended for binary GII-BCH codes if every other iteration of the nested KES is skipped to reduce the latency. Two instead of one higher-order syndromes need to be incorporated into each nested KES iteration and this makes the implementation much more challenging. In this paper, algorithmic reformulations and architectural modifications are developed to eliminate the clock frequency bottleneck and reduce the area of GII-BCH nested KES. Additionally, the number of processing elements is substantially reduced by analyzing the minimum number of coefficients to keep for the involved polynomials without undesirable degradation on the error-correcting performance. The critical path of the proposed scaled nested BCH KES architecture with reduced processing elements is only one multiplier and three adders. For an example GII-BCH code over ${GF}(2^{12})$ that has a ${t}_{v}=58$ -error-correcting code as the most powerful code generated by the nesting, our design also further reduces the area by 33%. [ABSTRACT FROM AUTHOR]

In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%. [ABSTRACT FROM AUTHOR]

This paper presents a compact and low-power time-domain CMOS temperature sensor intended for Internet of Things. To eliminate the off-chip reference clock that is commonly needed for time-domain CMOS temperature sensors, a precise on-chip reference clock is designed to measure the temperature-dependent delay generated by an inverter chain with even stages. In the reference clock circuit, a relaxation oscillator showing discharging phases with negative temperature coefficient (TC) is designed, which are compensated by 2 identical inverter-chains with positive-TC delay, resulting in a reference clock with nearly temperature-independent pulse width and period. In addition, a $2^{{\text {nd}}}$ -order hybrid time-voltage delta-sigma ($\Delta \Sigma $) modulator with feedforward path is proposed to quantize the temperature-dependent delay of the main inverter chain, achieving 100-mK resolution only in about 25-ms conversion time. Fabricated in 0.18- $\mu \text{m}$ CMOS, measurement results show that the best (worst)-case temperature accuracy of the clock’s reference time is ±0.015% (±0.055%) and the temperature sensor achieves a maximum inaccuracy of +0.66/−0.73 °C from −20 °C to −80 °C. The prototype occupies 0.45-mm2 chip area and consumes 1.99- $\mu \text{W}$ from a 1.8-V supply at room temperature. [ABSTRACT FROM AUTHOR]

This paper presents a calibration-free and low-jitter phase-locked loop (PLL) with small performance degradation over PVT. We introduce an open-loop discrete-time phase noise cancellation (OPDTPNC) technique to achieve a wideband filtering and circuit inner-gain-tracking for PVT stabilization. The OPDTPNC is an effective phase realignment that enables a filtering bandwidth ~1/4 of the reference clock frequency. Besides, with the common structures and PVT tracking bias for sampler and corrector of the OPDTPNC, the prototype PLL maintains its low jitter under a wide range of PVT variations. Eventually, by cascading a Type-II PLL with the OPDTPNC, the proposed hybrid PLL attains the benefits of both Type-II PLL and injection-locked clock multiplier (ILCM). Fabricated in 28-nm CMOS with an active area of 0.023mm2 it consumes 4.1 mV from a 1 V supply with a reference spur of -63 dBc. The measured rms jitter of the 2.4 GHz PLL is 248 fs and 686 fs with and without OPDTPNC, respectively. When the temperature, supply and loop gain vary from 0 to 100°C, ±5%, and 6dB, respectively, the jitter performance only degrades less than 9%. [ABSTRACT FROM AUTHOR]