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This paper presents a fully differential capacitance sensor employing the CBCM technique to map differential input capacitances into rail-to-rail differential output voltages. The circuit has been designed for measuring capacitances in the ±25-if range, appropriate for sensing live cells using on-chip microelectrodes. An array architecture based on a shielded current routing bus has been developed for incorporating the capacitance measurement circuit into sensor arrays, with each pixel comprising four minimum-size digital transistors, enabling high-density integration. In addition to improving spatial resolution, the shielded current bus also eliminates the need for individual pixel calibration, conserves sensor evaluation speed, and provides protection from junction leakage. The sensor employs a 3-phase clocking scheme that enables on-chip gain tuning. The paper also presents a modified version of the sensor circuit incorporating floating-gate transistors for mismatch compensation and output offset cancellation, performed using a combination of impact-ionized channel hot electron injection and Fowler-Nordheim tunneling mechanisms. Chips comprising both versions of the sensor circuits in test arrays employing the shielded current routing bus were fabricated in a commercially available 2-poly, 3-metal, 0.5-μm CMOS process. The sensor operation was demonstrated by measuring on-chip test capacitances comprising single and interdigitated metal electrodes, configured using different capacitance compensation schemes. The differential sensor in combination with the shielded current bus exhibits a maximum sensitivity of 200 mV/fF, a resolution of 15 aF, and an output dynamic range of, 65 dB. [ABSTRACT FROM AUTHOR]

Successive-Approximation-Register (SAR) Analog- to-Digital Converters (ADC) have been shown to be suitable for low-power applications at aggressively scaled CMOS technology nodes. This is desirable for many mobile and portable applications. Unfortunately, SAR ADCs tend to incur significant area cost and reference loading due to the large capacitor array used in its Digital-to-Analog Converter (DAC). This has traditionally made it difficult to implement large numbers of SAR ADC in parallel. This paper describes a compact 8b SAR ADC measuring only 348\ \mum\times 7\ \mum. It uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array; moreover, the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead. Any DAC error made during pDAC operation can be recovered later by an additional switching phase. Prototype measurements in 0.18 \mum technology shows that the DAC's figure-of-merit (FoM) is reduced from 61.3 fJ/step to 39.8 fJ/step by adopting pDAC switching with no apparent deterioration in Fixed-Pattern Noise (FPN) and thermal noise. [ABSTRACT FROM PUBLISHER]

The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr ⩽ 2 √LgCd. Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ⩾ 2 √LgCd. The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ≈ 2 √LgCd, referred to as the equivalent transition time for resonance. [ABSTRACT FROM AUTHOR]