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This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm2. The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported. [ABSTRACT FROM AUTHOR]

This paper deals with global synchronization problem of multiple discrete-time Markovian jump memristor-based neural networks (DTMJMNNs) with mixed mode-dependent delays via a novel event-triggered impulsive coupling control (ETICC). The parameters of the multiple DTMJMNNs and the mixed time delays (both discrete and distributed delays) switch randomly according to a Markov chain. In the ETICC strategy, the controller does not work all the time, but only works at impulse instants determined by specific events. In particular, the coupling matrix can be non-Laplacian. By using the Lyapunov stability theory, linear matrix inequalities (LMIs), and the Kronecker product, some sufficient conditions for global synchronization of multiple DTMJMNNs under the event-triggered strategy are derived. Two examples are presented to test the validity of the theoretical analysis results. [ABSTRACT FROM AUTHOR]

Although the cyber-physical system stability is widely studied, scholars focus more on system stability with communication time delay. Therein, grid-connected inverters with the digital control system are regarded as one simplest and typical cyber-physical system. Meanwhile, the switching/sampling frequency of the inverter is always selected as low as possible from an efficiency viewpoint, resulting in unavoidable delay time. This delay time is apt to cause the system instability, which is more prone to severity under weak grid. To this end, this paper provides a minimum switching/sampling frequency for grid-connected inverters. Firstly, the system impedance model with equivalent delay time is constructed, which is based on padé approximate approach. This equivalent delay time consists of three parts, i.e., sampling delay time in cyber/physical level, calculation delay time in cyber level and pulsewidth modulation delay time in physical level, which reflects the cyber-physical interaction impact. Furthermore, the stability forbidden criterion is applied to make the switching/sampling frequency solving process become Hurwitz matrix identification problem through space mappings. Based on these space mappings, an adaptive step search approach is adopted to obtain the minimum switching/sampling frequency. Finally, the proposed approach can well evaluate the system stability under different frequencies through simulation and experiment. [ABSTRACT FROM AUTHOR]

This paper aims to investigate the event-based extended dissipative state estimation problem for memristor-based Markovian neural networks in the presence of hybrid time-varying delays and sensor nonlinearity. To tackle the effect caused by information latching, sudden interference and environmental variation, the Markov jump model is employed to describe the memristor-based neural network. Besides, an event-triggered scheme is introduced to economize the cost of communication. Then some novel conditions are presented, which guarantee that the augmented error system is stochastically stable with an extended dissipative performance. The existence criterion of the desired mode-dependent estimator is also obtained in terms of linear matrix inequalities. Finally, simulation results are provided to show the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper addresses the finite-time event-triggered control problem for nonlinear semi-Markovian switching cyber-physical systems (S-MSCPSs) under false data injection (FDI) attacks. Compared with the traditional time-triggered mechanism, the proposed event-triggered scheme (ETS) can effectively avoid network resource waste. Considering the network-induced delay in the modeling, a closed-loop system model with time delay is established in the unified framework. By the use of a mode-dependent piecewise Lyapunov-Krasovskii functional (LKF), stochastic finite-time stability (SFTS) criteria are established for the resultant closed-loop system. Then, some solvability conditions are established for the desired finite-time controller in light of a linear matrix inequality framework. Finally, an application example of vertical take-off and landing helicopter model (VTOLHM) is provided to demonstrate the effectiveness of the theoretical findings. [ABSTRACT FROM AUTHOR]

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3–12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC 0.18 μm BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved. [ABSTRACT FROM AUTHOR]

This paper develops fundamental limits of digital phased arrays and proposes to use this as a map for the future technology investment in this area. Phased arrays, which are becoming ubiquitous in everything from vehicles, to communication systems including cell phones, to drones, satellites, and of course military applications. There is a recent trend toward digital phased arrays where each element in the antenna array is digitized. This allows monolithic integrated circuit integration as well as providing new capability due to digital signal processing. Digital phased arrays are increasingly being implemented with reconfigurable logic. Digitization and reconfigurability comes at a cost of power, which is increasingly becoming the limitation in these systems. This paper develops the fundamental energy limits of digital computation, applies this to phased arrays, and discusses directions for potential future digital phased array development. [ABSTRACT FROM AUTHOR]

Ring amplifiers are an advantageous new amplifier architecture, but designing them needs to be done in a time consuming process using manual transient simulations. AC based design criteria are of limit usability, because of their large signal operation. This paper presents an alternative design approach for ring amplifiers. A set of cost functions and parameters is developed and the parameters’ effect on the amplifier’s stability, accuracy and power consumption is explained in detail. The optimization process is derived from a simple ring-amplifier model and a stability criterion. This criterion is analyzed in the context of circuit parameters, design constraints and other ring-amplifier designs. A new battery-based self-biased ring-amplifier architecture is introduced and the first stage integrator of a switched-capacitor Delta-Sigma modulator is realized using the described ring-amplifier architecture. The proposed optimization process is successfully performed using 180 nm and 40 nm technology nodes (second node with two supply voltages) and the three designs are analyzed and compared. The optimization process is derived from a basic ring-amplifier model and can be applied to other ring-amplifier structures. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique for single slope analog to digital converter (SSADC) to suppress the row-wise noise in CMOS image sensor. A sample switch is used in the current-steering DAC to reduce the noise introduced by bias circuits, which will deteriorate the characteristic of uniformity in the row direction. The sample switch can fix the voltage which biases the current source in the current-steering DAC when generating a ramp to avoid the ramp fluctuation in the time domain. The digital correlated double sampling is used to reduce the non-uniformity in column-level ADCs. The CMOS image sensor prototype is fabricated in 110nm 1P3M process. The 10-bit SSADC achieves DNL of −0.20 / +0.15 LSB and INL of −1.35 / +0.91 LSB at a sampling frequency of 29.2 KHz. It is proved that the row-wise noise is reduced from $764~\mu {\mathrm {V}}_{\text {rms}}$ to 163 $\mu {\mathrm {V}}_{\text {rms}}$ at a frame rate of 228 fps using the proposed sample switch structure. The prototype photos taken by the sensor show that the row-wise noise is reduced under the low-illumination circumstance effectively. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step. [ABSTRACT FROM AUTHOR]

This paper presents an active rectifier operating at 40.68 MHz for wirelessly powered biomedical implant devices. The commonly used current-injection-based compensation and delay-based compensation schemes are analyzed. To tackle design difficulties at high frequency, a hybrid delay-compensation scheme is proposed to compensate for the turn-on and turn-off delays. The proposed scheme has a simple control logic that results in a power-efficient comparator design. A fully integrated active rectifier was fabricated in a standard 0.18- $\mu \text{m}$ CMOS process with a total area of 1.581 mm2 and a maximum output power of 56.6 mW. With the input ac voltage ranging from 2.5 to 4 V and the load resistor ranging from $200~\Omega $ to 2 $\text{k}\Omega $ , the measured peak voltage conversion ratio and peak power conversion efficiency reach 91% and 80.9%, respectively. [ABSTRACT FROM AUTHOR]

Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and sub-ns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/($\mu $ mV), which is an $1.7\times $ improvement on the next best reported level shifter for this type of application. [ABSTRACT FROM AUTHOR]

In this paper, we propose a flexible and reconfigurable changeable-radix fast Fourier transform (FFT) hardware architecture. It aims to support 48 different FFT sizes and up to 4096 FFT points, which are defined in current 3GPP-LTE communication system. The built-up design structure is primarily constructed on a radix-52 basis of single-path delay feedback FFT and up to 18 various changeable radixes of FFT processing. A design technique of switchable FIFO usage approach is developed to efficiently manage FIFO arrangement for 48 FFT modes. In addition, a design technique of coarse and fine rotating is designed to effectively reduce twiddle-factor circuit area. By using TSMC 40-nm CMOS technology, an FFT ASIC implementation only has a core area occupation of 0.414 mm2 and consumes 49.8 mW in average at maximal working frequency of 526.32 MHz. This innovative design work is competitive as compared to current state-of-the-art works, especially in terms of circuit area cost and power/energy performance evaluation. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the convergence properties of the max-consensus protocol in presence of asynchronous updates and bounded time delays on directed static networks. The work is motivated by real-world applications in distributed decision-making systems, for which max-consensus is an effective paradigm. The main result of this paper is that the strongly connectedness of the directed communication network is a sufficient condition for the asynchronous max-consensus protocol to let a distributed system converge in finite time. Implementation issues are also taken into account, by complementing the theoretical analysis with the definition of a mechanism to detect convergence in a distributed fashion. Finally, a numerical example is given, highlighting both the issues related to the failure of synchronous protocols applied to asynchronous settings and the effectiveness of the proposed asynchronous framework. [ABSTRACT FROM AUTHOR]

The almost sure finite-time sliding mode control issue is investigated for Markov jump systems. The switching asynchronism between the constructed controller and considered systems is studied. The influence of time-varying delays and disturbances on systems is fully considered, and the sliding mode controller design within a finite time interval is extended to the probability framework. First, the finite time interval is divided into the reaching and the sliding motion phases, and the almost sure finite-time boundedness is analyzed in both phases. Second, the sliding mode controller gain is determined by the provided linear matrix inequality-based criteria. Finally, a numerical example and DC-DC buck converter circuit example verify the effectiveness and less conservativeness of our method. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage and power-efficient 10 bit successive-approximation register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a time-domain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm2. At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3~\mu \text W to 2.5~\mu \text W and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]

OpenFlow, the main protocol for software-defined networking (SDN) advocated by Google, requires multiple flow tables with long and variable rule lengths. For fast packet forwarding, using ternary content-addressable memory (TCAM) as implementation of lookup-table has displayed superior performance in executing the conventional packet classification algorithms. However, applying traditional TCAM designs to an OpenFlow switch leads to problems of insufficient word length, inflexible table configuration, and high-power consumptions. This paper presents a low-power dynamic reconfigurable TCAM design for OpenFlow-compliant packet processing. It can support long and variable word lengths for different flow tables, with less than 5% of area overhead. To reduce dynamic power consumption without sacrificing throughput, the proposed hybrid-pipelined structure based on NAND-NOR CAM and pipelined-TCAM, can achieve lower energy-delay products than traditional TCAM. Moreover, the proposed self-power gating technique controlled by the mask data optimizes both NAND and NOR core cells, which lowers power consumption without additional control and routing overhead. Finally, the low-power reconfigurable TCAM is implemented in TSMC 40 nm CMOS technology. The implementation results show that the energy metric of the proposed reconfigurable TCAM is only 0.177 fJ/bit/search, at a 416 MHz operating frequency. Thus, the proposed TCAM design is very suitable for the emerging high performance packet processing in future SDN applications that need long and variable word lengths. [ABSTRACT FROM PUBLISHER]

The mutual exclusion element is a fundamental component of asynchronous arbiters. Despite their importance, however, the testability of these components is typically limited to functional testing. This paper discusses why this is not sufficient and investigates three MUTEX implementations, two of which are completely new, that support the test of the metastability filter part of the components. Additionally, we quantify the cost of the testable designs by comparing them to a baseline design in terms of failure rate, impact on MTBF, propagation delay, test power and area. Our experimental results show that testable MUTEXes increase area from 21% to 63% over the baseline implementation, but have a small impact on delay and provide a range of choices where testability, MTBF, test power and area can be traded-off against circuit and system requirements. [ABSTRACT FROM PUBLISHER]

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s. [ABSTRACT FROM AUTHOR]

This paper proposes a new timing storage circuit based on memristors. Its ability to store and reproduce timing information in an analog manner without performing quantization can be useful for a wide range of applications. For continuous-time (CT) digital filters, the power and area costly analog delay blocks, which are usually implemented as inverter chains or their variants, can be replaced by the proposed timing storage circuits to delay CT digital signals in a more efficient way, especially for low-frequency biomedical applications that require very long tap delays. In addition, the same timing storage circuits also enable the storage of CT digital signals, extending the benefits of CT digital signal processing (DSP) to applications that require signal storage. As an example, a 15-tap CT finite impulse response (FIR) Savitzky-Golay (S-G) filter was designed with memristor-based delay blocks to smoothen electrocardiographic (ECG) signals accompanied with high-frequency noise. The simulated power consumption under a 3.3-volt supply was 6.63 \muw. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 \mum show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3\times, 19\times, 29\times respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations. [ABSTRACT FROM AUTHOR]

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths. [ABSTRACT FROM AUTHOR]

Power management of mobile digital systems-on-chip necessitates large voltage regulation performances. DC/DC converters used to supply digital cores are facing stringent constraints with respect to load transients, reference tracking and accuracy. The fast transient response offered by sliding-mode control is well suited to DC/DC converters with fast varying load. Fixed switching-frequency is also mandatory for EMI and noise related issues. Fixed-switching frequency sliding-mode control has been experimented as a multi-loop system. There is a necessity to investigate the stability when multi-loops interact and the parameter set for each loop is quite large. The paper details a methodology for the stability analysis of a frequency-controlled sliding-mode DC/DC converter. The proposed stability analysis takes the possible cross-interactions into account and can be used to optimise the DC/DC controller without the limitations of a non-interaction criterion. As a verification a DC/DC converter is implemented in CMOS 130 nm. Experimental results agree with the analysis main recommendations. [ABSTRACT FROM AUTHOR]

This article shows a focus on the positivity and stability of Cohen-Grossberg-type time-delay memristor neural networks. We start by providing the existence and unique theorem of solutions for time-delay memristor neural networks to the case of unbounded delays. It is clear to find that the discriminate criterion of the existence and uniqueness of solutions about the argumented system with unbounded delays plays an important role in other related unbounded time-delay systems. Leveraging the Lyapunov method along with memristor nonlinearity, sufficient and necessary conditions for positivity and stability of Cohen-Grossberg-type memristor neural networks under unbounded delays are gained. Our proposed criteria don’t need any strictly restrictive conditions. These theoretical results derived here will be helpful to understand the convergence performance of memristor electrical systems. [ABSTRACT FROM AUTHOR]

The paper is concerned with the problem of input-to-state stability (ISS) for nonlinear delay systems with large delay periods (LDP). The concepts of the length rate of LDP and the frequency of LDP are introduced. First the considered system is converted into a switched delay system which may include an unstable subsystem. Then based on a piecewise Lyapunov functional, the ISS properties of the systems are developed under the constraints of the length rate and the frequency of LDP. ISS for a special kind of nonlinear delay systems is also considered and the conditions of nonlinear matrix inequalities (NLMIs) are proposed to guarantee the ISS properties of such a system. A numerical example and an example of a series DC motor are given to show the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

Clock gating is very useful for reducing the power consumed by digital systems. Three gating methods are known. The most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It unfortunately leaves the majority of the clock pulses driving the flip-flops (FFs) redundant. A data-driven method stops most of those and yields higher power savings, but its implementation is complex and application dependent. A third method called auto-gated FFs (AGFF) is simple but yields relatively small power savings. This paper presents a novel method called Look-Ahead Clock Gating (LACG), which combines all the three. LACG computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. A closed-form model characterizing the power saving per FF is presented. It is based on data-to-clock toggling probabilities, capacitance parameters and FFs' fan-in. The model implies a breakeven curve, dividing the FFs space into two regions of positive and negative gating return on investment. While the majority of the FFs fall in the positive region and hence should be gated, those falling in the negative region should not. Experimentation on industry-scale data showed 22.6% reduction of the clock power, translated to 12.5% power reduction of the entire system. [ABSTRACT FROM AUTHOR]

In this paper, the synchronization problem is investigated for a class of nonlinear delayed dynamical networks with heterogeneous impulsive effects. The intrinsic properties of heterogeneous impulses are that impulsive strengths are inhomogeneous in both time and space domains, i.e., the impulsive effect in each node is not only nonidentical from each other, but also time-varying at different impulsive instants. The purpose of the addressed problem is to derive synchronization criteria such that, the nonlinear delayed dynamical networks with heterogeneous impulses can be synchronized to a desired state. By means of a time-dependent Lyapunov function and the comparison principle, several sufficient conditions are established under which nonlinear dynamical networks with heterogeneous impulsive effects are exponentially synchronized to a desired state. An example is given to show the effectiveness of the proposed results. [ABSTRACT FROM AUTHOR]

This paper presents an asynchronous digital technique for the realization of an integrator that takes as input the time-difference between two rising edges of digital signals and produces a corresponding time-difference output signal. The key element of this circuit is a time-memory cell called TLatch. This circuit has the ability to store the time-difference between two edges and allow its retrieval at a later time. By using two TLatches in parallel, a dual-path high-throughput integrator is proposed. Internal mismatches in delays can be removed using a simple calibration algorithm that aligns the frequency of two internal oscillators, thereby eliminating the need for trimming or any reference element. The proposed architecture is fabricated in 1.2 V 0.13-μm IBM CMOS technology and the experimental results confirm the integration operation. [ABSTRACT FROM PUBLISHER]

In this work, we present an asynchronous MTJ-CMOS hybrid system with extremely fine-grained voltage scaling (EFGVS) technique. The supply voltage of the system is turned on/off by asynchronous bundled-data handshake signals. The MTJ write circuit is variation robust, self-terminated and redundant-write preventing. Besides, EFGVS and asynchronous data driven handshake enhance the timing robustness by removing the matching delay elements and reducing timing assumptions. The completion detection circuitry is also simplified. A RISC processor with proposed techniques is designed and fabricated by 55nm technology. The voltage supplies are turned on/off within tens of picoseconds. The energy for writing MTJs is 0.45pJ. The tolerance of the minimum TMR due to process variation is 75%. Sleep mode leakage power can be reduced over 10 $\times$ by powering off modules with the Break-even Time of 23.6 ns. Because of the extremely fine-grained voltage scaling, no more than 20% of the modules are powered on during the execution. [ABSTRACT FROM AUTHOR]

This work presents a 28GHz reflection type transmission-line (TL) based phase shifter. The proposed architecture employs a completely passive approach to double the phase shift achievable using a TL when compared to conventional architectures. The phase shifter, along with a preceding low noise amplifier and buffer, is implemented in a 65nm CMOS process. The fabricated chip achieves a measured phase resolution of 11.25° at 28GHz, with an rms error of 3° and a total phase shift of 180°. The insertion loss of the phase shifter alone is 17dB. The active area of the entire phase shifter, including LNA and buffer is 0.41mm2. [ABSTRACT FROM AUTHOR]

A high-speed dynamic biasing technique is presented for reducing op amp power in discrete-time, multistage, analog circuits employing op amp sharing. To exploit typical power scaling in such circuits, a charge pump, of which the on-times of up and down currents are controlled by two comparators, performs rapid change of the op amp bias condition between a low-current mode and a high-current mode during nonoverlapping clock periods of the two phase clocks. The errors caused by finite comparator delay are compensated for by embedding intentional offset voltages in the comparators, which are implemented by using asymmetric differential input pairs in the comparators. To verify the efficacy of the proposed biasing technique, an 11-b pipelined analog-to-digital converter (ADC) has been implemented using 0.15- \mu \textm devices in a 28-nm CMOS technology. With a 20-MHz sampling clock, the ADC achieves a 61.8-dB SNDR while consuming a 2.24-mW power from a 1.8-V supply. The MDAC and ADC power are reduced by about 45% and 30%, respectively, compared with a conventional pipelined ADC employing an op amp in each MDAC. Owing to the simple structure of the proposed dynamic biasing, the prototype ADC occupies only 0.052 mm2. [ABSTRACT FROM AUTHOR]

An energy-efficient fast array multiplier is proposed and designed. The multiplier operates in a left-to-right mode enabling a full overlap between reduction of partial products in carry-save form and the final addition producing the product. The design is based on the left-to-right carry-free (LRCF) multiplier. It differs from the LRCF multiplier in a much smaller on-the-fly conversion circuit of $O(n)$ size and the use of radix-4 full adders in the conversion. The new converter produces the most-significant half of the product during the reduction process. It eliminates the most-significant part of the final adder. The least-significant half of the product is obtained with a carry-ripple adder during the reduction. Thus conversion of the carry-save form of accumulated partial products to the conventional product does not add any delay to the total time of the multiplier. Several right-to-left, left-to-right multipliers and tree multipliers are designed for 16, 24, 32, and 56 bits, and radices 2 and 4, synthesized in 90 nm technology and compared, demonstrating the advantages and disadvantages of the proposed design with respect to area, delay, power, and energy. We considered both truncated and full-precision multipliers. The proposed multiplier has lower delay, area, power, and energy than other considered types of array multipliers. Its advantages grow with the increase in precision. As expected, it is slower than a tree multiplier but it has smaller area, power, and energy. [ABSTRACT FROM PUBLISHER]

An 8 b 700 MS/s 1 b/cycle asynchronous successive approximation register (SAR) analog to digital converter (ADC) which skips comparator metastability is presented. A delay-shift technique is proposed to shift the delay of comparator to generate a 1.5 b redundancy range and to accelerate comparison speed. This reduces the settling requirement and compensates for the dynamic offset by redundancy. The prototype ADC in 40 nm CMOS technology achieves an SNDR of 43.9 dB at Nyquist rate and consumes 5 mW with a 1.2 V supply. This results in an FoM of 56 fJ/conversion-step. Due to no extra calibration circuit, the core circuit occupies an area of only 0.006 \textmm^2. [ABSTRACT FROM AUTHOR]

In today's process technologies, power supply noise may cause serious clock jitter and circuit malfunction. Noise occurs by the fast and simultaneous voltage switching. A primary contributor to the noise is the clock-tree and the underlying sequential circuits that switch simultaneously, thus causing high current peaks. This work proposes to spread the switching of the clock-tree drivers, while maintaining low skew at the sinks of the tree, where the clocked circuits are connected. Driver switching characterization has been used for fast computation of peak currents, delays and slopes, integrated in a two-phase algorithm. It first constructs the clock-tree in a top-down traversal, employing a mix of high threshold voltage (HVT) and weak low threshold voltage (LVT) clock-drivers. A bottom-up delay correction phase then takes place, aiming at clock skew minimization. The algorithm was implemented in 40 nanometers TSMC process technology, achieving 35% to 70% clock-tree peak current reduction, translated to similar reduction in power supply noise. The proposed method can easily be combined with other existing methods to further reduce the noise. [ABSTRACT FROM AUTHOR]