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In this paper, hybrid dynamical systems theory is applied to the analysis and control of switched converters with Pulse-Width Modulated (PWM) inputs. The system is described by a state-space model with continuous flows and discrete jumps, without averaged equations. The modulation effects are captured in full without using time-dependent signals, by enlarging the state vector to include the PWM waveform generation process. Furthermore, the sample-and-hold mechanism associated with the sampling frequency is also taken into account with this approach. A control law is proposed based on a Lyapunov function candidate. Furthermore, convergence sets and the steady state jitter, inherent to PWM-based controllers, are analyzed estimating limit sets for the augmented state. Consequently, output chattering can be bounded. By using hybrid dynamical system theory, the control designer gains a deeper understanding of the effect of modulation in the closed-loop dynamics, avoiding the problems associated with the use averaged models. Experimental results validate the proposed method. [ABSTRACT FROM AUTHOR]

The growth of IoT applications requires DC-DC converters to have small printed circuit board (PCB) areas and high efficiency over a wide load range. A multi-mode operation of DC-DC converters, therefore, is often necessary to achieve this high efficiency over a wide load range. This paper introduces a tri-mode DC-DC buck converter for IoT applications. The tri-mode operation with PWM, PFM, and multiple-sawtooth PWM (MSPWM) modes helps to retain the high efficiency over the wide load range. The MSPWM mode also enhances a noise margin of the converter, ensuring a regular switching operation at an ultra-light load condition. With a load current prediction scheme, the proposed tri-mode converter requires neither additional load current sensor nor multiple mode controllers. In addition, a soft-start operation is employed to prevent an in-rush current. The proposed tri-mode buck converter has been fabricated through a 0.18- $\mu \text{m}$ CMOS process with a chip area of 0.97 mm $\times0.88$ mm. A load-dependent seamless mode transition is realized, and a maximum converter efficiency of 91% has been measured with a 7.4-MHz switching frequency. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

This paper proves a novel sampling theorem with constant amplitude and variable width pulses. The theorem states that any bandlimited baseband signal within \pm0.637 can be represented by a pulsewidth modulation (PWM) waveform with unit amplitude. The number of pulses in the waveform is equal to the number of Nyquist samples and the peak constraint is independent of whether the waveform is two-level or three-level. The proof of the sampling theorem uses a simple iterative technique that is guaranteed to converge to the exact PWM representation whenever it exists. The paper goes on to develop a practical matrix based iterative technique to generate the PWM waveform that is guaranteed to converge exponentially. The peak constraint in the theorem is only a sufficient condition. In fact, many signals with higher peaks, e.g., lower than Nyquist frequency sinusoids, can be accurately represented by a PWM waveform. [ABSTRACT FROM PUBLISHER]

Active pulse-width-modulated (PWM) voltage rectifiers are commonly used to convert ac power from a three-phase grid to a regulated dc voltage with unity input power factor. The output voltage regulation is normally achieved by an outer voltage feedback loop and a sinusoidal pulse-width-modulated (SPWM) inner current loop. Due to output voltage disturbances, such as those produced by a capacitive load, the inner current loop can be easily driven into over-modulation and possible six-step operating regions. Current research efforts have focused on extending the linearity of the modulated voltage in the over-modulation range to reduce the input current harmonics and on studying the closed-loop stability via conventional small-signal linearization around a fixed operating point. Such linear techniques obviously fall short of predicting large-signal transient stability. In this paper, catastrophic bifurcation of the three-phase voltage-source converter is reported. The physical origin of the phenomenon is identified. Boundaries of catastrophic bifurcation in the parameter space are derived. The phenomenon has been verified experimentally. [ABSTRACT FROM PUBLISHER]

This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs. [ABSTRACT FROM PUBLISHER]

While a host of analysis techniques exist to perform steady-state analysis of open-loop converter systems, solutions for close-loop converter systems are distinctly more challenging to obtain. Analysis is done either via computationally intensive time-domain simulation or through reliance on a disconnected collection of published iteration techniques. Moreover, most of these iteration techniques deal with a system containing only one or two converters. This is not adequate to deal with a smart grid or microgrid system, which consists of multiple (more than two) converters. This paper proposes a generalized and systematic solution procedure to obtain the steady state of a system containing multiple closed-loop power converters, in a computationally efficient manner. The solution procedure consists of a general five step approach that can easily be applied to a wide variety of power converter systems. It is shown that numerous previously proposed methods may be viewed as specific implementations of the generalized systematic procedure. A new solution approach, suitable for analysis of tightly coupled multiconverter networks, is developed based on the generalized solution procedure. Results of the new approach are validated against PSCAD/EMTDC simulations for a representative multiconverter network. [ABSTRACT FROM PUBLISHER]

We combine 2-tap feed-forward amplitude equalization with phase equalization by 4-tap integrated pulse-width modulation. In a $\text{V}_{\mathbf {SS}}$ -terminated transmitter, amplitude equalization is selected for pull-up data transmission, and phase equalization for pull-down data transmission, and the strength of equalization can be controlled depending on channel losses. This combines the strength of amplitude equalization with the energy efficiency of phase equalization. A prototype quarter-rate transmitter for memory interfaces, fabricated in a 65nm CMOS process, performed single-ended signaling at a data-rate of 16Gb/s/pin over a channel with a loss of 14.7dB. Its energy efficiency is 1.04pJ/bit/pin and the figure-of-merit is 0.070pJ/bit/pin/dB. [ABSTRACT FROM AUTHOR]

Class-D amplifiers switch high voltages and currents at high frequencies and hence produce electromagnetic interference (EMI). This work presents a technique to reduce the high frequency ripple, which is still present after the output filter. A Class-A ripple reduction amplifier is put in parallel to the output of the Class-D amplifier, each having their own feedback loop with digital filters. High ripple reduction loop gain is achieved at the PWM frequency by using a resonator as digital loop filter. Dissipation in the Class-A amplifier is reduced by using a low common-mode signaling technique. Common-mode and differential-mode switching components at the PWM frequency are reduced by 27 dB and 18 dB respectively. Total system efficiency is 79% at 40 W output power. [ABSTRACT FROM AUTHOR]

We propose a novel low-harmonics low-noise modulation scheme for switched-mode dc–dc converters. The proposed scheme is a hybrid of a randomized modulation scheme, namely, the randomized wrapped-around pulse position modulation scheme (RWAPPM), and a noise-shaper. The RWAPPM mitigates the switching-frequency harmonics in the input current, whereas the noise-shaper mitigates the low-frequency noise therein. We derive an analytical expression for the input current spectrum of the hybrid scheme. We benchmark the hybrid scheme against the conventional pulse width modulation scheme (PWM) and the RWAPPM without the noise-shaper. At 0.5 duty cycle, 3.3-V input voltage, 100-kHz average switching frequency, and with the second-order noise-shaper, the peak spectral power in the input current spectrum of the hybrid scheme is 18.1 dB lower than the PWM. Other randomized and spread-spectrum modulation schemes, in general, have undesirably higher input noise current than that of the PWM. However, the input noise current of the proposed hybrid scheme, obtained at ~73-mA rms (integrated over a 200-kHz bandwidth without an input filter), is comparable with that of the PWM, and is lower by ~16-mA rms compared with that of the RWAPPM without the noise-shaper. We also benchmark the hybrid scheme against other well known randomized and spread-spectrum modulation schemes. We further propose a novel pulse generator structure that embodies the hybrid scheme. We realize a dc–dc converter employing the pulse generator, and measure the converter to verify the derived expression and the characteristics of the hybrid scheme. We also measure the output voltage spectrum, the transient-response, and the operating range of the converter. [ABSTRACT FROM PUBLISHER]

Models of inverters and other converters based on averaging have been widely used in numerous simulation applications. Generalized averaging can be applied to model both average and switching behavior of converters while retaining the faster run times associated with average-value models. Herein, generalized average models for single- and three-phase pulse width modulation inverters are proposed. These models are based on a quasi-Fourier series representation of the switching functions that includes fundamental and switching frequency components as well as sideband components of the switching frequency. The proposed models are demonstrated both in simulation and experimentally and are found to accurately portray both the fundamental and the switching behavior of the inverter. In particular, the use of sideband components allows accurate representation of the variation in switching ripple magnitude that occurs in the steady state. The generalized average models are found to have simulation run times that are significantly faster than those associated with detailed models. Therefore, the proposed generalized average models are suitable for simulation applications in which both accuracy (including the switching behavior) and fast run times are required (e.g., long simulation times, systems with multiple converters, and repeated simulations). [ABSTRACT FROM AUTHOR]

A floating buck controlled multi-mode dimmable light-emitting diode (LED) driver that uses a stacked NMOS switch is presented, which reduces static operational current and eliminates auxiliary winding to simplify design and cost. The accuracy of the output current benefits from the use of a line-voltage compensation technique which can mitigate the effect of line-voltage fluctuation on current consistency. The proposed LED driver is implemented in 0.5 \mum 5V/40 V backend 2P2M CMOS process and occupies a die size (with pads) of 1.17\times 0.84\ mm^2. The experimental results show that the proposed LED driver achieves peak power efficiency of 95.4% across a wide range of input voltage from 85 to 264 Vac and a wide range of series-connected load LEDs from 11 to 27. The worst-case line regulation and load regulation of the output current are 0.28% and 0.25%, respectively. Measurements further show that the startup time is only 34.8 ms at 220 Vac with 50 Hz-input and multi-mode dimming can be easily implemented. [ABSTRACT FROM AUTHOR]

A time-invariant multi-frequency modeling technique is proposed for pulse-width-modulated (PWM) dc-dc converters. The proposed methodology distinguishes between different types of modulation carrier signals (e.g., sawtooth and isosceles triangle carriers). A straightforward systematic procedure is proposed to automatically convert the conventional state-space time-variant model to the proposed time-invariant model. Hence, high-order time-invariant models can be easily developed for system design and stability analysis purposes. Closed-loop time-domain and open-loop frequency-domain responses extracted from a laboratory-scale Cuk converter have verified the proposed methodology. [ABSTRACT FROM PUBLISHER]

A new scheme of a gain/efficiency-improved serial- parallel switched-capacitor converter (SPSCC) is proposed by combining an adaptive-conversion-ratio (ACR) and pulse-width- modulation (PWM) control for step-up DC–DC conversion. For improving gain, the power part consists of one mc-stage cell and one nc-stage cell in cascade to obtain the step-up gain of (mc+1)\times(nc+1) at most. For improving efficiency, the ACR control with adapting stage number m,n is presented to select a proper gain of (m+1)\times(n+1) (m=1,2,\ldots,mc, n=1,2,\ldots,nc) according to the desired output. Further, the PWM control is adopted to enhance output regulation as well as robustness to source/loading variation. Some theoretical analysis and control design include: formulation, steady-state analysis, conversion ratio, efficiency, output ripple, stability, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a SPSCC prototype, and all results are illustrated to show the efficacy of this scheme. [ABSTRACT FROM PUBLISHER]

A three-state signal coding scheme is proposed for driving Class-S amplifiers with higher efficiency than conventional techniques. The approach is formulated in the framework of polar modulation, where the magnitude is controlled by a timing code that specifies positive and negative rectangular pulses as well as a third zero state, and the phase is varied by modulating the clock delay. In particular, high efficiency is attained when the active pulse widths are a half-cycle of the carrier frequency, and the zero-state is formed by skipping pulses. In this case, full-amplitude modulation has the same efficiency as a Class-D amplifier, and is only slightly degraded as the amplitude is decreased. In addition, the technique operates at only 2\times sampling and is very simple to implement. Spectral analysis is performed for baseband signals consisting of single tones, 2-tone suppressed-carrier, and bandlimited random noise. The latter case emulates real communication signals and is shown to exhibit good spectral characteristics and low error-vector magnitude in the time domain. An important application of this technique is in all-digital, power-efficient power amplifiers for cellular base stations and handsets. [ABSTRACT FROM PUBLISHER]

An output voltage ripple aware design of different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is presented. A mathematical analysis has been carried out to model the output voltage ripple of random switching converter. Simulations of the converter have been undertaken and measured results from the converter fabricated with a standard 0.35 \mum CMOS process verify the proposed design approach. From experimental results, a carefully designed ramp can reduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance and capacitance comparing to the conventional design. [ABSTRACT FROM AUTHOR]

We propose a time-domain technique that significantly improves resolution of an RF-DAC. As an alternative to resorting to various resolution improvement attempts in the amplitude domain or through quantization noise shaping, pulsewidth modulation (PWM) of a single unit switching device is employed with fine timing accuracy easily afforded by advanced CMOS technology. The PWM is categorized into centered PWM and noncentered PWM depending on the relative pulse position, and their performance and implementation methods are compared. The technique is examined in the context of a commercial EDGE polar transmitter realized in 65 nm CMOS, which employs an amplitude modulator with basic 10-bit amplitude resolution limited by the RF-DAC switching device mismatches. The proposed architectures with centered PWM and noncentered PWM achieve the worst case resolution improvement of 2.2 bits and 2.5 bits, respectively, assuming 20-ps worst case time granularity of the PWM signal controls. [ABSTRACT FROM PUBLISHER]

A dual modulation technique to improve power conversion efficiency with minimal increase in output voltage ripple is presented. The worsening switching noise caused by parasitic resistance and inductance due to high-switching operation can also be alleviated by the proposed ac ripple detector. Furthermore, the dual modulation method can speed up the load transient response since the switching frequency can increase to 5 MHz during the transient period. At very light loads, the switching frequency is always kept higher than the acoustic frequency to avoid noisy sound. Experiment results show that the converter operates at 5 MHz using a small inductor of 1 \mu \H. The load transient response time is shorter than 3 \mu \s when load current changes from 150 to 450 mA or vice versa. Power efficiency is kept higher than 85% over a wide load current range. Specifically, light efficiency can be raised to about 45% above that of the conventional design. [ABSTRACT FROM PUBLISHER]