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In this paper, a technique for slew-rate (SR) boosting suitable for switched-capacitor circuits is proposed. The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals. The proposed architecture employs simple circuitry to detect the need for a large output current by employing a highly sensitive pre-amplifier followed by a class-B amplifier. The functionality of the class-B transconductance amplifier is dictated by a predefined hysteresis, and operates in parallel with the main amplifier. The proposed solution demands small static power (under 20% of main amplifier power) due to its class-B nature. The experimental results in a 40-nm CMOS technology show more than 45% reduction in slew time, and a 28% shorter slew time for 1% settling time when used in a typical 4.5 bit/stage block commonly used in pipelined analog-to-digital converters. Compared with the core amplifier, HD3 at 500 MHz reduces by more than 10 dB when the SR boosting circuit is activated. [ABSTRACT FROM AUTHOR]

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is shared among multi channels. The dual-sampling architecture for the output amplifiers also reduces the power consumption of the column driver IC, where the operating time of the time-shared DAC and the output amplifier is efficiently handled during the limited 1-horizontal time. The sampling accuracy of the dual-sampling architecture is improved by a simple dummy switch and a source follower. The proposed time-shared DAC with the dual sampling is implemented by a 0.13- $\mu \text{m}$ high-voltage complementary metal-oxide-semiconductor process and integrated in a 960-channel column driver IC, while the effective channel area of the column driver IC is 5520 $\mu \text{m}^{2}$. As a result of driving an 11-inch-wide quad extended graphics array AMOLED panel by using the prototype column driver IC, the panel uniformly generates a clear image. [ABSTRACT FROM AUTHOR]

Chopping is a technique to reduce offset and flicker noise in amplifiers by up-converting them to higher frequency, and subsequently filtering them out. A typical chopping implementation uses two complementary phases which have a finite non-overlap time in between them. When such a chopping phase is used in the first integrator of a continuous-time delta sigma modulator, the non-overlap time can significantly degrade two key parameters of the modulator’s performance—in-band noise and its inherent anti-aliasing. In this paper, we develop a model to include the effects of non-overlap duration on the modulator’s performance. Then this model is used to derive analytical expressions for in-band noise and anti-aliasing for a given non-overlap duration. The results obtained are verified using simulation. [ABSTRACT FROM AUTHOR]

This paper presents a systematic method to analyze $N$ -path mixers and filters consisting of periodically switched $RC$ -networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint network for simplified analysis of the harmonic transfer functions that describe the signal transfer and folding. Moreover, harmonic transfer cancellations due to the $N$ -path implementation with $N$ equal capacitors switched by $N$ non-overlapping clocks are systematically analyzed. The method is applied to a recently published $N$ -path filter-mixer combination and verified by simulations. [ABSTRACT FROM AUTHOR]

Linear periodically time-varying (LPTV) circuits are finding increased prominence in reconfigurable transceiver applications. Impedance matching of such circuits to the antenna impedance is essential for fully on-chip receiver topologies. However, deriving the $S_{11}$ of an LPTV circuit is non-trivial in general. Moreover, reflections at harmonic offsets from input frequencies can also be expected due to the time-varying nature of the circuit. This paper utilizes the conversion matrix-based analysis technique to compute the $S_{11}$ of a general LPTV circuit. Furthermore, it is shown that signal reradiation at harmonic shifts from input frequencies is also obtained as a natural consequence of this analysis. Examples related to mixer-first receivers, switched-capacitor receiver front-ends (with reset), and Filtering-by-Aliasing (FA)-based receivers are considered to verify the analysis. Design guidelines are provided to attain optimal $S_{11}$ in a few such scenarios. Explicit analytical expressions are derived for reradiation in ideal $N$ -path mixer-first receivers and FA-based receivers, while guidelines are provided for proper choice of conversion matrix expressions/sizes in case of numerical computation. [ABSTRACT FROM AUTHOR]

This paper deals with the observer-based adaptive sliding mode control (OBASMC) design for nonlinear uncertain singular semi-Markov jump systems. The system satisfies the singular property and follows a stochastic semi-Markov process related to Weibull distribution. Due to the influence of sensor factors in practical systems, the state vectors are not always known. Additionally, the unavoidable measurement errors in the actual system always lead to the model uncertainties and the unknown nonlinearity. Our attention is to design the OBASMC law for such a class of complex systems. First, by the use of the Lyapunov–Krasovskii functional, sufficient conditions are given, such that the sliding mode dynamics are stochastically admissible. Then, the OBASMC law is proposed to guarantee the reachability in a finite-time region. Finally, the practical system about dc motor model is given to verify the validity. [ABSTRACT FROM AUTHOR]

An integrated, power-saving SAR analog-to-digital converter suitable for image sensor applications is presented in this paper. In comparison with previous works, the proposed, build-in passive correlated double sampling (CDS) and programmable gain amplifying (PGA) technique is superior in power, as it achieves correlated noise cancellation and signal amplification without additional OTAs. Furthermore, inspite of a single-ended signal from the image sensor array, single-ended-to-differential sampling is used to enable symmetrical DAC switching. The adopted LSB-first algorithm, utilizing the strong correlation between neighboring pixels, significantly reduces the energy and number of bitcycles per conversion. Additionally, a comparator with four inputs is adopted to keep the DAC array unchanged, avoiding power consumption from the operation of the initial guess for next quantization. Fabricated using a 65-nm process, the 10-bit ADC occupies a die area of 0.19 mm2. The measured DNL and INL are less than +0.68/−0.45 LSB and +1.07/−1.15 LSB, respectively. Operating at 40 MS/s, the ADC provides an SNDR of 55.7 dB and SFDR of 70.9 dB for signal bandwidths of 17.2876 MHz and consumes $415.2~\mu \text{W}$ from a 1.2-V power supply, resulting in a figure of merit of 21.7 fJ/conversion-step. Additionally, the CDS and PGA functionality are verified to be effective in removing reset level influence and providing gains of −6 dB, 0 dB, and 6 dB. [ABSTRACT FROM AUTHOR]

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the high side and low side on-resistance according to the input voltage, is used. To maximize the output power, a maximum power point tracking circuit is designed to track the internal source resistance. Radio frequency (RF) kick-up and low voltage startup are used to improve the cold start voltage. The proposed converter is implemented in a 0.18- $\mu \text{m}$ standard CMOS process, which occupies a chip area of about 0.48 mm2. Measurement results show that the peak efficiency of the converter can be up to 90.8% and 60% at 180 and 20 mV of the open-circuit voltage, respectively. Owing to the cold startup circuit, the proposed converter can start successfully with 260-mV open-circuit voltage or −16-dBm RF input. Moreover, the open-circuit voltage can be further lowered to 12 mV with 1.5- $\mu \text{W}$ output power after startup. [ABSTRACT FROM AUTHOR]

Memristor is considered as a promising circuit element which can be used in many applications. Various synthesis methods for Boolean functions have been explored in the literature using memristor-based design styles. Memristor crossbar is considered as one of the most preferred structures for implementing logic functions as well as memory. In this paper, a general synthesis flow has been proposed using the MAGIC logic design style to map multioutput Boolean functions to memristor crossbars. The functions are realized as a netlist of NOR and NOT gates. Two alternate methods of evaluating the gates are used, serial and parallel, which give a tradeoff between the number of cycles and the size of the crossbar. A strategy for scheduling the gates to time steps has also been proposed to reduce the hardware overhead. The switching delays and energy requirements are estimated using SPICE simulation. Synthesis results are reported for ISCAS’85 benchmark functions that show an average reduction of 68.8% in the number of cycles, 52.8% in energy consumption, and 96.4% in the number of memristors required as compared to a very recently published work. [ABSTRACT FROM AUTHOR]

This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a sampling capacitor. To address both mismatches along with other mismatches residing in TI-ADCs, this papers utilizes least-squares (LS) minimization technique in order to extract mismatch parameters while injecting a sinewave at two distinct frequencies. Programmable capacitor arrays (PCAs) are used to tune the bandwidth of sampler, and correcting buffer bandwidth mismatch is performed in digital-domain. The method presented here is scalable to arbitrary number of interleaved paths, and can easily be combined with existing calibration methods for gain, offset, and timing-skew mismatches. Numerical experiment via Monte-Carlo simulations demonstrates significant performance improvement in the spurious-free dynamic range (SFDR) from 38 dB to 75 dB for a 32-channel time-interleaved ADC model that includes all major mismatches. [ABSTRACT FROM PUBLISHER]

This paper deals with the analysis of the convergence properties of the max-consensus protocol in presence of asynchronous updates and bounded time delays on directed static networks. The work is motivated by real-world applications in distributed decision-making systems, for which max-consensus is an effective paradigm. The main result of this paper is that the strongly connectedness of the directed communication network is a sufficient condition for the asynchronous max-consensus protocol to let a distributed system converge in finite time. Implementation issues are also taken into account, by complementing the theoretical analysis with the definition of a mechanism to detect convergence in a distributed fashion. Finally, a numerical example is given, highlighting both the issues related to the failure of synchronous protocols applied to asynchronous settings and the effectiveness of the proposed asynchronous framework. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

This paper presents a $W$ -band (92–100 GHz) phased array receive channel adopting a power domain vector modulator (VM), which utilizes a 90° hybrid-coupler-based phase interpolator. The quadrature hybrid leverages its inherent functions of quadrature phase splitting and power combining to interpolate phases by combining the weighted signals from variable gain amplifiers in the power domain. Compared with prior active VMs, in the proposed VM, the phases are synthesized in a pure passive network with a matched impedance, less vulnerable to circuit nonlinearity. The distributed 90°-hybrid coupler offers a wideband operation of quadrature phasing and phase interpolation, resulting in a low phase error over the $W$ -band. The measured VM peak-to-peak gain variation for all 5-bit phase states is 7.7–11 dB at the expense of 31-mW dc power from 2.2-V supply voltage. The measured rms gain error is <1.6 dB over 93–108 GHz and the rms phase error is <1.5° at 94 GHz. The output $P_{-1\,{\mathrm{ dB}}}$ is −4 dBm at 94 GHz at the highest gain state. In the receive channel employing the 90°-hybrid-based VM, the peak-to-peak gain variation is 23–26 dB with 9.3–11-dB NF at the expense of 50-mW dc power from 2.2-V supply voltage. The measured input $P_{-1\,{\mathrm{ dB}}}$ is −26 dBm. The chip size of the receive channel, implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process, is $1.65\times0.55$ mm $^{\vphantom {R^{l}}2}$. [ABSTRACT FROM AUTHOR]

Considering the coupling relationships between transfer power and efficiency in continuous-mode inductive power transfer (IPT) systems, this paper presents a pulse energy injection inverter for IPT systems. With a new topology and parameters tuning, the pulse energy injection IPT system with the proposed inverter can work in switch-mode to decouple transfer power with efficiency. Moreover, the transfer power is only decided by the duty ratio of the semiconductor switch, rather than affected by the transmitting resonator, receiving (Rx) resonator, and load. In this way, the pulse energy injection IPT system holds an operating frequency much lower than the resonant frequency to reduce switch loss and improve transfer efficiency. Experiments verify that the IPT system with proposed inverter maintains a high level efficiency within the middle range and realizes nearly 80% supply to load transfer efficiency even in a weak coupling coefficient ( $k=0.044$ ). Finally, experimental analysis implies that the pulse energy injection inverter is suitable for full-range transmission, and high-Q IPT systems with uncertainty in Rx circuits or load. [ABSTRACT FROM AUTHOR]

Wiring is one of the main challenges in aircrafts. The avionics industry is exploring new schemes to minimize the number of power and data cables to build lighter, more reliable and fuel-efficient aircrafts. In this paper, we describe a novel integrated power harvesting interface to procure power required for avionic sensors. The implemented power harvesting approach is based on a modified power over Ethernet scheme in which the power in the ARINC 825 field (data) bus during its idle times serves as the source for the power conversion chain. A transistor-level design is carried out in CMOSP 0.35 \mu \textm (AMS) 3.3 V/5 V technology and the system performance is investigated under various conditions to improve its efficiency. From the experimental tests, an overall efficiency of 60 % was achieved and the harvesting device provided an output power of 10.08 mW for feeding sensors. Reported experimental results proved that the proposed power recovery scheme could serve as a power recovery unit to supply embedded sensors. [ABSTRACT FROM PUBLISHER]

Switch $R-C$ passive $N$ -path mixers and filters enable interference-robust radio receivers with a flexibly programmable center frequency defined by a digital multi-phase clock. The radio frequency (RF) range of these circuits is limited by parasitic shunt capacitances, which introduce signal loss and degrade noise figure. Moreover, the linear periodically time varying nature of switch $R-C$ circuits results in unwanted signal folding which needs to be suppressed by linear time- invariant (LTI) prefiltering by passive LC filters. This paper analyzes the interaction between capacitive or inductive LTI prefiltering and an $N$ -path mixer or filter, leveraging an analysis technique based on the impulse response of the adjoint network. Previously reported results for an inductive source impedance are derived in a simpler fashion, while providing circuit intuition. Moreover, new results for $N$ -path receivers with a shunt capacitor, and a combination of a series inductor and shunt capacitor are derived, as well as design criteria to minimize loss and frequency shifting in the peak response of these circuits. [ABSTRACT FROM PUBLISHER]

This paper addresses the event-based leader-following consensus of a class of multi-agent systems with switching networks. Fully distributed event-triggered functions are proposed to select the sampling instants automatically. Detailed algorithms are given to design the feedback gains and coupling strength. The positive lower bound of the sampling intervals is captured to exclude Zeno behaviours. Finally, simulations are also carried out to verify the effectiveness of the event-triggered control scheme. [ABSTRACT FROM PUBLISHER]

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz. [ABSTRACT FROM PUBLISHER]

Every year, smarter and more complex attacks compromise electronic systems. Unauthorized access to the secure keys stored within nonvolatile memories is a concerning problem affecting secure applications. This paper presents an RRAM architecture secured against firmware and physical attacks. If a hack attempt occurs, and taking advantage of the threshold behavior of fast RRAM devices, this solution erases the whole memory in a single process preventing the sensitive information to be accessed while avoiding the circuit destruction. Complementing encryption solutions, our architecture provides extra-protection mechanisms that, even deprived from the main power supply, prevent the most sensitive information to be leaked. [ABSTRACT FROM PUBLISHER]

We reconsider the black box model by Urbanek of electric-arc in air-blast circuit breakers or in circuit breakers characterized by an electro-negative gas (e.g., SF6) as quenching medium. It has the unique characteristic to account for the dielectric breakdown that possibly reignites the arc. We show some of its main features that have been almost hidden from the first publication of the model in the literature. The conductance in the Urbanek model plays two roles: 1) it effectively represents the conductance of the burning arc when positive and 2) it is a thermodynamic indicator when negative. This thermodynamic indicator is used to eventually trigger a restrike of the arc. We show that this switching behavior can be formally analyzed by considering the model as an hybrid dynamical system. In this paper, we reconsider it and show its main dynamic properties through some case studies. [ABSTRACT FROM PUBLISHER]

The cooperative output regulation problem for singular multi-agent systems subject to static networks was studied recently under the assumption that each follower system satisfies the standard assumption. In this paper, we further study the same problem for singular multi-agent systems subject to jointly connected switching networks. First, by introducing a static output feedback control, we remove the unnecessary standard assumption on the singular system in the existing result. Then, we derive a reduced-order normal multi-agent system and obtain a distributed output measurement feedback control law based on the existing result on the normal multi-agent system. Finally, we show that the composition of the static output feedback control law and the distributed output measurement feedback control law solves the cooperative output regulation problem for the original singular multi-agent system. Our result enlarges the class of systems whose cooperative output regulation problem is solvable. [ABSTRACT FROM AUTHOR]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is based on one-time characterization via micromagnetic multi-domain simulations, overcoming the inaccuracies introduced by single-domain analysis, which most of the existing frameworks are based on. As further distinctive capability, non-Gaussian stochastic variations of the MTJ write switching time are explicitly modeled through a Skew Normal distribution, making the model suitable for low-power and low-voltage designs. The framework involves the use of a Verilog-A look-up table-based model, which assures easy integration with commercial design tools. Our strategy is evaluated on a spin-transfer torque-magnetoresistive random access memory (MRAM) working in RAM and true random number generator (TRNG) modes. In RAM mode, while the commonly-used approach based on Gaussian-distributed switching statistics tends to underestimate the pulse width required for a write error rate of 10^-6 by about 20%, our Skew Normal-based strategy allows tracking reference micromagnetic results with an average error less than 4%. In TRNG mode, our approach also allows a better tracking of the reference 50%-switching probability contour with an error less than 1%abs. However, the incorporation of the Skew Normal distribution in our Verilog-A model results in an increase of the CPU time by 50% on average as compared with the use of the built-in statistical functions. [ABSTRACT FROM AUTHOR]

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

In this paper, a modified switched transconductor mixer structure is proposed to realize a low-power, low-noise, and wideband mixer, in which, a transconductor stage with fixed dc operating point is switched by the ac-coupled local oscillator (LO) signal. In this way, only a small LO signal is required to turn the transconductor ON and OFF, and thus a low-power LO buffer can be used to achieve wideband down-conversion. To further expand the bandwidth, the inductive peaking technique is used at the RF port to eliminate the capacitive loading effect resulted from the input transistors. As the noise power from LO stage appears in common mode at the mixer output, good noise performance is realized, too. Additionally, output distortion-cancellation IF buffer is added to facilitate the testing. Fabricated in the 0.13- \mu \textm CMOS process, 15.5–17.5-dB gain and 4–5.2-dB noise figure are achieved in 1–10-GHz bandwidth. The mixer core consumes a low power of 8.3 mW from 1.5-V supply, and the whole chip consumes 22.3 mW, including the IF buffer. The active chip area is less than 0.2 mm2. [ABSTRACT FROM PUBLISHER]

This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]

Motivated by the concept of circuit design in digital circuit, this paper proposes a one-dimensional (1D) nonlinear model (1D-NLM) for producing 1D discrete-time chaotic maps. Our previous works have designed four nonlinear operations of generating new chaotic maps. However, they focus only on discussing individual nonlinear operations and their properties, but fail to consider their relationship among these operations. The proposed 1D-NLM includes these existing nonlinear operations, develops two new nonlinear operations, discusses their relationship among different nonlinear operations, and investigates the properties of different combinations of these operations. To show the effectiveness of 1D-NLM in generating new chaotic maps, as examples, we provide four new chaotic maps and study their dynamics properties from following three aspects: equilibrium point, stability, and bifurcation diagram. Performance evaluations are provided using the Lyapunov exponent, Shannon entropy, correlation dimension, and initial state sensitivity. The evaluation results show that these new chaotic maps have more complex chaotic behaviors than existing ones. To demonstrate the performance of 1D-NLM in practical applications, we use a pseudo-random number generator (PRNG) to compare new and existing chaotic maps. The randomness test results indicate that new chaotic map generated by 1D-NLM shows better performance than existing ones in designing PRNG. [ABSTRACT FROM PUBLISHER]

Emerging technologies have enabled efficient, high-speed realizations of ultra-dense crossbar arrays, driving the need for better insight in the transient operation of such systems. Previous work focused mostly on the effect of line resistance and its impact on steady-state response. In this paper, we develop a compact $RC$ framework that includes the effects of parasitics. We use memristors as an exemplar device where interconnect parasitics (resistance, inductance, capacitance, and conductance) are extracted using ANSYS Q3D extractor for 5- and 50- $nm$ feature sizes. A model for the crossbar is presented, considering the stray and coupling capacitive parasitics of the crossbar. The derived model is based on state-space representation and provides more insight into the behavior of crossbar arrays containing either linear or nonlinear switching devices. The framework provides a closed-form solution to evaluate Elmore delay, as well as the steady-state response of the system. Signal delay is evaluated and compared for both grounded and floating interconnect inputs and verified against HSPICE, showing a perfect match. [ABSTRACT FROM PUBLISHER]

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- \mu \textm standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC’s loading of the previous stage is reduced by using a single-ended structure, and by eliminating the largest capacitor in the array. The common mode voltage of the input signal can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with an asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 – \mu \textm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB, and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from 0.75-V supply voltage. [ABSTRACT FROM PUBLISHER]

This paper describes a 2.4-GHz digitally-modulated class-D polar power amplifier (PA) with novel circuit techniques to enhance the average power-added efficiency (PAEave) that becomes increasingly crucial to prolong the battery lifetime. The PA features 5+5-b interactive AM-AM modulation between the class-D unit amplifiers and a novel high resolution dynamic matching network (DMN) to improve the back-off PAE. A novel power-gating technique tailored for class-D PAs is also proposed and embedded into each unit amplifier and its driver (tapped inverter chain), alleviating leakage-current suppression, area reduction of the DMN, and direct-powering by a standard 1.5-V AA battery. An high back-off power efficiency is made possible by introducing a multi-bit capacitively-tuned DMN, which adds low loss while improving the PAE of the unit amplifiers using the load-pull optimization. The DMN also can correct the antenna impedance mismatch for better average Pout (Pout,ave) and PAEave under a practical VSWR (2.5:1), and aids to reconfigure the PA between the Pout-optimized and the PAE-optimized modes. For a 20-MHz 64-QAM OFDM output at a typical EVM (< −25 dB), the 65-nm CMOS PA exhibits 40.7% PAEave at a 16.3-dBm Pout. The mode switching is demonstrated as a prospective function for battery lifetime extension. [ABSTRACT FROM AUTHOR]

Recent innovations in software defined CMOS radio transceiver architectures heavily rely on high-linearity switched-RC sampler and passive-mixer circuits, driven by digitally programmable multiphase clocks. Although seemingly simple, the frequency domain analysis of these linear periodically time variant (LPTV) circuits is often deceptively complex. This paper uses the properties of sampled LPTV systems and the adjoint (inter-reciprocal) network to greatly simplify the analysis of the switched-RC circuit. We first derive the transfer function of the equivalent linear time-invariant filter relating the input to the voltage sampled on the capacitor in the switched-RC kernel. We show how a leakage resistor across the capacitor can be easily addressed using our technique. A signal-flow graph is then developed for the complete continuous-time voltage waveform across the capacitor, and simplified for various operating regions. We finally derive the noise properties of the kernel. The results we derive have largely been reported in prior works, but the use of the adjoint network simplifies the derivation, while also providing circuit insight. [ABSTRACT FROM PUBLISHER]

The instrumentation systems for implantable brain–machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a $\Delta \Sigma $ SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0–2MASH topology. This configuration uses a specialized FIR window to decimate the $\Delta \Sigma $ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using $0.18\,\mu $ m CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm2 silicon footprint. Moreover, a 14fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2 Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications. [ABSTRACT FROM PUBLISHER]

This paper, split into Parts I and II, reviews recent innovations in circuit design that have accelerated the miniaturization of sensor nodes. Design techniques for key building blocks, such as sensor interfaces, timing reference, data communication, energy harvesting, and power management are reviewed. In particular, Part I introduces analog circuit techniques and sensor interfaces for miniaturized sensor nodes. The energy budget of such system is highly restricted due to the small battery volume. Therefore, ultra-low power design techniques are critical enablers and are reviewed. Design techniques for compact monolithic integration are also discussed. [ABSTRACT FROM PUBLISHER]

Resistive RAM (RRAM) technologies are gaining importance due to their appealing characteristics, which include non-volatility, small form factor, low power consumption, and ability to perform logic operations in memory. These characteristics make RRAM highly suited for Internet of Things devices and similarly resource-constrained systems. This paper proposes a novel memristor-based xnor gate that enables the execution of xnor/xor function in the memristive crossbar memory. The proposed two-input xnor gate requires two steps to perform the xnor function. The design of the circuit utilizes bipolar and unipolar memristors and permits cascading by only adding an extra step and one computing memristor. To the best of our knowledge, this is the first native stateful xnor logic implementation. Spice simulations have been used to verify the functionality of the proposed circuit. This includes benchmarking the proposed design against the state-of-the-art stateful memristor-based logic circuits. The results for implementing three-input xor using the proposed circuit demonstrate efficient performance in terms of energy, latency, and area. The gate shows 56% saving in energy, 54% less number of steps (latency), and 50% less number of computing MR (area) compared with the state-of-the-art stateful xor/xnor implementations. [ABSTRACT FROM PUBLISHER]

In this paper, a novel thermoelectric energy harvesting system with a reconfigurable array of thermoelectric generators (TEGs), which requires neither an inductor nor a flying capacitor, is proposed. The proposed architecture can accomplish maximum power point tracking (MPPT) and voltage conversion simultaneously via the reconfiguration of the TEG array, and demonstrate significantly improved power conversion efficiency over the conventional switching converter and switched-capacitor architectures. Two systematical scaling approaches—powers-of-two scaling and maximum-factor scaling—are presented and analyzed to serve as the design guideline, catering for reconfigurable TEG arrays of different sizes. In order to optimize the chip area required, a custom-designed, multi-level hierarchy and systematically scalable switch array that requires a reasonable number of switches is also developed to enable the reconfiguration of the TEG array. The 16-node and 12-node versions of the proposed system have been implemented in a standard 0.35- \mu \textm CMOS process. Measurement results verify the analysis, and confirm that the proposed system can maintain a higher than 88.8% efficiency over a wide range of temperature gradients. [ABSTRACT FROM PUBLISHER]

Memory-centric computing with on-chip non-volatile memories provides unique opportunities for native and local information processing in an energy-efficient manner. Design and modeling methodology based on resistive random access memory (RRAM) is presented in this paper. A hierarchical RRAM SPICE model having different levels of physics realism is described, where the incorporated stochasticity provides a more accurate representation of RRAM operations. Three in-memory operation schemes are developed and experimentally verified for reconfigurable in-memory logic, using RRAM built in 3-D vertical structure (i.e., 3-D RRAM). As a case study for RRAM-centric computing systems, we evaluate the Please note that there were discrepancies between the accepted pdf [TCAS_R1_combined.pdf] and the [TCAS_RRAM-centric computing_hli_FINAL_submit.docx] in the lines 12 and 70. We have followed [TCAS_RRAM-centric computing_hli_FINAL_submit.docx]. use of 3-D RRAMs for a language recognition system using the hyperdimensional (HD) computing model. Utilizing the inherent properties of 3-D RRAM, we demonstrate, using fabricated 3-D RRAM integrated with FinFET, the essential kernels for HD operations: multiplication, addition, and permutation (MAP). RRAM-centric HD systems exhibit strong resilience to hard errors induced by RRAM endurance failures, making a promising case for using various types of RRAM for memory-centric HD systems. [ABSTRACT FROM PUBLISHER]

An efficient micro-scale solar power management architecture for self-powered Internet-of-Things node is presented in this paper. The proposed architecture avoids the linear regulator and presents a complete on-chip switched capacitor-based power converter in order to achieve higher end-to-end efficiency. Unlike traditional architectures, where the harvested energy processes twice, the proposed architecture processes the harvested energy only once before it reaches to the load circuit, irrespective of the ambient conditions. The system efficiency has been improved by ~12% over the traditional architecture. The entire power management system has been designed using 0.18- \mu \textm CMOS technology node, and the circuit simulations demonstrate that the proposed architectural changes bring in a system efficiency of 82.4% under different light conditions. In addition to that, a hardware setup is created using commercially available ICs and photovoltaic cells, to validate that the proposed power management system is practically realizable. [ABSTRACT FROM PUBLISHER]

Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with the strict design requirements of portable devices. Due to the significant power consumption in the multiplier components of the FIR filter, various techniques aimed at reducing the switching activity of these multipliers have been proposed in the literature. However, these techniques rarely exploit the flexibility on the algorithmic level, which can lead to additional benefits. In this paper, FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime, while ensuring the full baseline performance of any programmed filter whenever it is required. The analyzed FIR filters were fabricated in a 28nm FD-SOI test chip and measured at a near-threshold, 600mV supply voltage. For example, by carefully choosing slightly perturbed coefficients in a low-pass configuration, power savings of up to 33% are achieved when accepting a 3dB degradation on the stopband, as compared with the baseline implementation of the filter. [ABSTRACT FROM PUBLISHER]

Nonlinear circuits may be synchronized with interconnections that evolve in time incorporating mechanisms of adaptation found in many biological systems. Such dynamics in the links is efficiently implemented in electronic devices by using memristors. However, the approach requires a massive amount of interconnections (of the order of N^2 , where $N$ is the number of nonlinear circuits to be synchronized). This issue is solved in this paper by adopting a memristor crossbar architecture for adaptive synchronization. The functionality of the structure is demonstrated, with respect to different switching characteristics, via a simulation-based evaluation using a behavioral threshold-type model of voltage-controlled bipolar memristor. In addition, we show that the architecture is robust to device variability and faults: quite surprisingly, when faults are localized, the performance of the approach may also improve as adaptation becomes more significant. [ABSTRACT FROM PUBLISHER]

In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies. [ABSTRACT FROM AUTHOR]

This paper presents a circuit in which tungsten oxide -based analog memristors are post-processed on a CMOS-based Field-Programmable Analog Array Integrated Circuit (FPAA-IC). FPAAs are powerful tools for rapid analog experimentation, prototyping and power-efficient computing, and they allow custom analog circuits to be built and reconfigured. The primary motivation for this work is to introduce and demonstrate the operation of the FPAA/memristor hybrid circuit and the board-level infrastructure, and to form a basis for subsequent empirical work on analog memristive computing. The experiments shown in this paper demonstrate a successful fabrication of memristors on the FPAA substrate, and the usefulness of the hybrid computing infrastructure in terms of experimentation with memristors. The experiments suggest that a single state variable cannot capture the adaptation of a memristor. To this end, a SPICE compatible memristor model with two state variables is presented. Furthermore, a memristor-based adaptive coincidence detector is demonstrated on the FPAA/Memristor computing infrastructure. [ABSTRACT FROM AUTHOR]

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$ control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the $D \ge0.5$ control does not allow $D$ to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows $D < 0.5$ without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3< CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively. [ABSTRACT FROM AUTHOR]

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, including on-chip reference buffers. [ABSTRACT FROM AUTHOR]

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with ‘memimpedace’ elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at $100^{o}C$ across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance’s quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses). [ABSTRACT FROM AUTHOR]

This article proposes a broadband high-efficiency parallel-circuit (PC) class-EF power amplifier (PA) along with a quarter-wavelength stub for the first time. By adding a reactive element ${X}$ , the design space is expanded so that the impedance terminations of the fundamental and harmonics are no longer fixed points. Based on the broadband capability of the proposed structure, using a GaN HEMT transistor, a proof-of-concept circuit implemented with the Chebyshev impedance transformation network is designed and fabricated. Experimental results demonstrate a high-efficiency broadband PA operating from 2.6-3.9 GHz, with the average efficiency of 71.5%, the measured output power (${P}_{\textit {out}}$) of 38.8-40.9 dBm and the power gain of 8.5-10.6 dB. [ABSTRACT FROM AUTHOR]

The almost sure finite-time sliding mode control issue is investigated for Markov jump systems. The switching asynchronism between the constructed controller and considered systems is studied. The influence of time-varying delays and disturbances on systems is fully considered, and the sliding mode controller design within a finite time interval is extended to the probability framework. First, the finite time interval is divided into the reaching and the sliding motion phases, and the almost sure finite-time boundedness is analyzed in both phases. Second, the sliding mode controller gain is determined by the provided linear matrix inequality-based criteria. Finally, a numerical example and DC-DC buck converter circuit example verify the effectiveness and less conservativeness of our method. [ABSTRACT FROM AUTHOR]

Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator. [ABSTRACT FROM AUTHOR]

This paper presents a 12b 180 MS/s 0.068 mm2 $2\times$ time-interleaved pipelined-SAR analog-to-digital conver-ter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a compact area. We improve the noise performance by implementing a merged-residue-DAC operation in the first-stage ADC. Also, we propose a dual-phase bootstrap technique to improve the sampling linearity in the partial interleaving architecture. The measurement results of the ADC prototype in 65 nm CMOS demonstrate the effectiveness of the proposed calibration through the enhancement of the signal to noise-and-distortion ratio from 51.5 to 60.9 dB at a Nyquist input, leading to a FoM@Nyq of 36.7 fJ/conversion-step. [ABSTRACT FROM AUTHOR]