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This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs. [ABSTRACT FROM PUBLISHER]

Class-D amplifiers switch high voltages and currents at high frequencies and hence produce electromagnetic interference (EMI). This work presents a technique to reduce the high frequency ripple, which is still present after the output filter. A Class-A ripple reduction amplifier is put in parallel to the output of the Class-D amplifier, each having their own feedback loop with digital filters. High ripple reduction loop gain is achieved at the PWM frequency by using a resonator as digital loop filter. Dissipation in the Class-A amplifier is reduced by using a low common-mode signaling technique. Common-mode and differential-mode switching components at the PWM frequency are reduced by 27 dB and 18 dB respectively. Total system efficiency is 79% at 40 W output power. [ABSTRACT FROM AUTHOR]

A three-state signal coding scheme is proposed for driving Class-S amplifiers with higher efficiency than conventional techniques. The approach is formulated in the framework of polar modulation, where the magnitude is controlled by a timing code that specifies positive and negative rectangular pulses as well as a third zero state, and the phase is varied by modulating the clock delay. In particular, high efficiency is attained when the active pulse widths are a half-cycle of the carrier frequency, and the zero-state is formed by skipping pulses. In this case, full-amplitude modulation has the same efficiency as a Class-D amplifier, and is only slightly degraded as the amplitude is decreased. In addition, the technique operates at only 2\times sampling and is very simple to implement. Spectral analysis is performed for baseband signals consisting of single tones, 2-tone suppressed-carrier, and bandlimited random noise. The latter case emulates real communication signals and is shown to exhibit good spectral characteristics and low error-vector magnitude in the time domain. An important application of this technique is in all-digital, power-efficient power amplifiers for cellular base stations and handsets. [ABSTRACT FROM PUBLISHER]

A dual modulation technique to improve power conversion efficiency with minimal increase in output voltage ripple is presented. The worsening switching noise caused by parasitic resistance and inductance due to high-switching operation can also be alleviated by the proposed ac ripple detector. Furthermore, the dual modulation method can speed up the load transient response since the switching frequency can increase to 5 MHz during the transient period. At very light loads, the switching frequency is always kept higher than the acoustic frequency to avoid noisy sound. Experiment results show that the converter operates at 5 MHz using a small inductor of 1 \mu \H. The load transient response time is shorter than 3 \mu \s when load current changes from 150 to 450 mA or vice versa. Power efficiency is kept higher than 85% over a wide load current range. Specifically, light efficiency can be raised to about 45% above that of the conventional design. [ABSTRACT FROM PUBLISHER]