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In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results. [ABSTRACT FROM AUTHOR]

This paper presents an area- and power-efficient dual-output switched capacitor (DOSC) dc–dc buck converter for wearable biomedical devices. The DOSC converter has an input voltage range between 1.05 and 1.4 V and generates two simultaneous regulated output voltages of 1 and 0.55 V. The DOSC consists of two main blocks: a switched capacitor regulator and an adaptive time multiplexing (ATM) controller. The switched capacitor regulator generates a single regulated voltage using pulse frequency modulation based on a predetermined reference voltage. In addition, the ATM controller generates two simultaneous output voltages and eliminates the reverse current using pulse width modulation during the switching between the output voltages. Addressing the reverse current problem is important to reduce the output voltage droop and improve the performance. The proposed converter supports load currents of 10– $350~\mu \text{A}$ and 1– $10~\mu \text{A}$ at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm2. Measured results show that a peak efficiency of 78% is achieved at a load power of $300~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

This paper presents a new method for detecting and reversing the polarity of a low-voltage thermoelectric generator (TEG) in inductor-based converters. The proposed technique makes use of the inductor response to a voltage change due to the flip in the TEG polarity. The inductor voltage provides two distinguishable states which correspond to the normal and the reversed TEG polarity. A switch matrix circuit is then used to correct the polarity by physically reversing the TEG connection. The detection circuit along with the switch matrix provide a positive input voltage from the TEG to the inductor-based converter. The proposed technique is an efficient polarity detection with all-digital implementation, fully integrated, small area and power overhead. The prototype chip is fabricated in 65-nm CMOS and occupies an area of 0.09 mm2. Measurement results confirm a maximum efficiency of 70% at 50 mV TEG voltage and 40~\mu \text A output current. The proposed technique is part of an autonomous thermal energy harvesting system that detects and corrects the TEG polarity. [ABSTRACT FROM AUTHOR]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub-\muW power sources is presented. For available input-power levels below 1 \muW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub-\muW energy harvesting circuit uses an area of 0.2 mm^2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 \muW. The circuit can harvest energy whenever the available power is more than 0.3 \muW. Efficiency at 0.3 \muW is 25%, at 0.5 \muW is 37% and at 1 \muW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV. [ABSTRACT FROM PUBLISHER]

Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]

A low energy-noise switched-capacitor (SC) sensor interface for resistive bridge sensor is presented. The SC amplifier achieves low-power metric with two operating modes using operation-phase-dependent biasing and compensation scheme in the op-amp design. This novel op-amp works in high-bandwidth high-power mode to sample the bridge signal for 13\mu \text s twice and in low-bandwidth low-power mode for 474\mu \text s over 500\mu \text s measurement interval. To further reduce the power of the SC amplifier in system level, a SC level-shift design is adopted. Regarding offset calibration, a capacitor divider based trimming scheme is implemented to generate the mid-point DC output voltage under the constraint of the feedback capacitor size. Implemented in 65 nm CMOS, the SC interface together with the regulator, voltage reference and trimming circuit occupies an area of 0.358 mm2. For the first test setup utilizing Half Wheatstone Bridge, the proposed SC amplifier consumes 12.3\mu \text W at 1 V regulated supply with a 2 kHz system clock. The measured Signal-to-Noise Ratio (SNR) of SC circuit is 55.6 dB. In the second test setup using a commercial sensor with 0.092 mV/kPa sensitivity, the interface has demonstrated the sensing function with sensitivity of 3.52 mV/kPa. Finally, compared to the representative prior-arts, this work has achieved the best energy-noise figure-of-merit at identical fractional resistance change. [ABSTRACT FROM AUTHOR]

Current mode control is widely used in the switching power supply designs because of its fast response and less stability concern. However its performance at light load condition is limited by the precision of current sensing. In this work, instead of using high speed current sensor, a frequency-locked loop (FLL) is incorporated to extend the operation range with high power efficiency using a single controller. The 1.8-V output DC-DC converter has been fabricated with a standard 0.35-\mu\ m CMOS process and supplied from 2.7 to 4.3 V. Experimental results show that this switching converter operates from 100 to 600 kHz with the efficiency higher than 90% for the load current between 25 and 450 mA. The output voltage ripple is smaller than 30 mV with a 4.7-\muH inductor and a 4.7-\muF capacitor. [ABSTRACT FROM AUTHOR]