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In this paper, a novel saturation-based control method is proposed for high-order sliding mode (HOSM) dynamics with upper-triangular nonlinearities. Firstly, a new HOSM dynamics with upper-triangular nonlinearities is constructed based on the traditional HOSM dynamics, so as to reduce the uncertainties in the control input channel. Then, a HOSM controller is established by means of the adding a power integrator method such that the new HOSM dynamics is locally stabilized. Finally, the saturation-based controller is constructed by a combination of the saturation technique and the local HOSM controller to guarantee that the sliding variables can converge into a domain of attraction in a finite time and retain inside it thereafter. The rigorous stability analysis is made by the Lyapunov theory. A simulation example is also given to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Soft-input soft-output (SISO) detector for the iterative detection and decoding of coded spatial modulation (SM) signals needs to compute the extrinsic bit log-likelihood ratio (LLR) associated with each detected bit. The maximum logarithmic maximum a posteriori (max-log-MAP) detector is known to perform closely to the optimal logarithmic maximum a posteriori (log-MAP) detector with much lower computational complexity. In this paper, we first apply several mathematical tricks to derive a new and low-complexity algorithm for the max-log-MAP detector. The proposed algorithm features a new tree pruning technique to visit few lattice points and a smart list administration technique to retain a max-log-MAP detector. By following the proposed algorithm, we then design a hardware architecture for SISO detection of coded SM signals over the scenario of 64-QAM symbols, 8 transmit antennas, and 4 receive antennas. Under the TSMC 40 nm CMOS technology, the VLSI implementation results reveal that our architecture requires 46.4K gates and leads to detection throughput 450 Mbps, while operating at clock frequency 400 MHz and consuming power 46 mW. Being the first hardware architecture for SISO detection of coded SM signals, our proposed low-cost max-log-MAP detector is very attractive. [ABSTRACT FROM AUTHOR]

The ultra-low hardware consumption feature of stochastic decoding has made it a potential candidate for the implementation of low-density parity-check(LDPC) decoders. However, the existing stochastic LDPC decoders still suffer from performance degradation and relatively high decoding cycles caused by the correlation among stochastic bit streams. In this paper, we propose Hybrid Stochastic(HS) decoding, which achieves high performance, high throughput, and high hardware efficiency by jointly using our proposed novel stochastic check node(CN) and Two’s Complement(TCS) variable node(VN) to realize Min-Sum Algorithm(MSA) and its enhancements. Fully correlated stochastic bit streams are used to entirely eliminate the indeterminacy caused by the correlation, which results in high performance and fast convergence and inherits the low complexity of stochastic decoders at the same time. We demonstrate the HS decoding by designing a (2048,1723) decoder in a 65 nm process, which achieves the highest Bit-Error-Ratio(BER) performance, highest throughput, and top hardware efficiency among existing stochastic LDPC decoders. We also demonstrate that HS decoding can achieve excellent decoding performance for different code rates and lengths 5G New Radio(NR) LDPC codes. Thus, HS decoding can be adopted in wide applications. [ABSTRACT FROM AUTHOR]

Efficient simulation of switched-mode power conversion circuits is necessary for the analysis and optimization of power electronics. This paper introduces the extended impedance method (EIM) to the simulation and analysis of general switched-mode power converter circuits. By using the EIM method, the conventional impedance concept can be extended to involve more linear time-variant (LTV) and nonlinear devices, such as MOSFET switches and diodes, which are commonly used in switched-mode power conversion circuits. EIM models a circuit network from the component level in the frequency domain, rather than from the system-level constitutive differential equation in the time domain. Compared with the conventional averaging method, EIM can reveal more high-frequency features of a switched-mode converter circuit, in particular, those around the switching instants. A buck converter is taken as a representative example to validate the EIM based analysis. Both the simulation and experimental results prove that EIM provides precise numerical results, which match the real waveform, as the commercial simulators, e.g. PSpice and ADS, do. Moreover, it largely reduces the computational complexity towards more efficient and more flexible steady-state analysis of switched-mode power electronics. [ABSTRACT FROM AUTHOR]

This paper presents a compact single-ended inverter-based transceiver with swing improvement for short-reach links. The low output impedance of the transmitter enlarges the output swing and the eye size to overcome large single-ended noise while relaxed impedance matching provides good signal integrity. For good area efficiency, the proposed transmitter utilizes an inverter driver which is much smaller than the conventional source-series termination driver and thus occupies only $42.5 ~\mu \text{m}^{2}$. By taking the advantage of a large signal swing, the receiver consists of only four slicers and latches to minimize area overhead and to simplify the design. The transceiver was fabricated in 28-nm CMOS technology and tested at supply voltage of 1.13 V. The transmitter achieved a large output swing of 850 mV, which is 50.4 % larger than the conventional source-series termination transmitter. At the far-end of a channel consisting of a 1 m SMA cable and a 17 mm printed circuit board trace, the transmitter achieved eye openings of 440 mV and 234 mV at 16 Gb/s (−2.7 dB) and 20 Gb/s (−8 dB), respectively. Even with a large switching noise of 100 mV, the in-situ eye at the receiver was measured 114 mV with 7.4 dB loss. [ABSTRACT FROM AUTHOR]

A new active building block namely, subtractor connected first-generation current conveyor (S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new quadrature oscillators (QOs) employing only one S-CCI are introduced as application examples. The introduced SFI employs two resistors with a single matching requirement and a grounded capacitor. Each of the introduced QOs has one grounded resistor, one floating resistor, and two grounded capacitors without any matching problems. Non-ideality analyses are performed. Furthermore, a third-order filter application is given. A layout of the S-CCI in $0.18 \mu \text{m}$ technology occupying the area of about $71\,\,\mu \text{m}\,\,\times 44\,\,\mu \text{m}$ is given. Also, numerous post layout simulations based on the SPICE program are accomplished. Moreover, several experiments are realized to confirm the theory. [ABSTRACT FROM AUTHOR]

High-quality data transmission synchronization process is frequently expected in light of secure communication mechanisms (SCMs), especially for space laser communication among the satellite constellation. To improve security and reliability during the data transmission processes prominently, control problems of chaotic synchronization synchronously at the same time are explored. In this paper, several novel error synchronization control protocols are proposed to solve these problems. First, by introducing a norm-normalized sign function (NNSF), unique (fixed-) time-synchronized stability is manifested, such that all non-zero state elements reach the origin synchronously at the same time. And upper bounds of synchronous resident time calculated by offered protocols are irrelevant/relevant to initial states of the error systems. Second, integrated with the (fixed-) time-synchronized stability theories, the (fixed-) time-synchronized sliding mode controllers with special convergent performance are established for two representative types of chaotic systems. Third, the ratio-persistent performance plays a dominating role for simultaneous convergence of the errors. Further, the innovation of the algorithms is reflected in that the decrypted signal is completely consistent with the transmitted message signal within synchronized settling time. Finally, in the simulation, not only theoretical verifications, but also practical verifications of image encryption and decryption processes verify the effectiveness of the SCMs. [ABSTRACT FROM AUTHOR]

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology. [ABSTRACT FROM AUTHOR]

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed. [ABSTRACT FROM AUTHOR]

This paper presents a full hardware implementation of a magnetic tunnel junction based stochastic tunable bitstream generator. It provides highly accurate control of the switching probability, while showing important robustness to process and temperature variations. We propose a new architecture of sensing scheme based on the pre-charged sense amplifier approach that uses an asynchronous digital module to control the internal signals of the sense amplifier with the purpose of improving the reliability against the timing hazards and reducing the power consumption by detecting the end of the reading to stop the required static currents. The circuit also features a digital feedback loop that analyzes the output bitstream and adapt the current in such a way that the bitstream encodes precisely the required probability. This circuit features an important bit generation rate at a low energy cost. Based on an exhaustive characterization of the circuit, we provide a behavioral description in Verilog, with timing and power files to be integrated as a standard cell in the digital design flow for application level evaluation of the performance. Thus, we also provide a design and evaluation flow from device to digital level of abstraction. [ABSTRACT FROM AUTHOR]

Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel-physics-based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of recurrent SNN using proposed low-power, low-area, and low-leakage band-to-band-tunneling (BTBT) based neurons. A low-power thresholding circuit is proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. The tunneling regime enables a high input impedance in the BTBT neurons (few $\text{G}\Omega$) to enable a voltage input without loading the synaptic array. To verify the effect of the proposed neuron, a 36-neuron recurrent SNN is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing. [ABSTRACT FROM AUTHOR]

A well-performed capacitive power transfer (CPT) system highly depends on its compensation to achieve load-independent (LI) output and zero phase angle (ZPA) operation. It is particularly meaningful to maintain these objectives under various misalignments. This paper is devoted to a general and comprehensive method to study and explore all the potential high-order compensations. The coupler parameter variation is evaluated under different types of misalignment, and misalignment-insensitive (MI) parameters are properly designed for MI resonance. A general and straightforward decomposition and synthesis method is then proposed to generate the high-order resonant tanks. With the help of inverse ABCD parameters, all tank candidates are further judged by their capability for LI output and ZPA operation. Finally, two example CPT systems are built to verify the LI output and ZPA operation under misalignment. [ABSTRACT FROM AUTHOR]

In this paper, we present an integrator-differentiator transimpedance amplifier (I-D-TIA) with a dc compensation, which incorporates widely tunable multi-element pseudo-resistors (MEPRs) in its dc servo loop and ac signal path. The implemented MEPR in the dc path is continuously tunable from $460 \,\mathrm {k\Omega }$ to $300 \,\mathrm {G\Omega }$ allowing the TIA to process dc currents with a dynamic range of more than $100 \,\mathrm {dB}$. The MEPR in the differentiator ac signal path provides a tunable resistance between $0.3 \,\mathrm {M\Omega }$ and $100 \,\mathrm {M\Omega }$ , resulting in an overall ac transimpedance between $3 \,\mathrm {M\Omega }$ and $1 \,\mathrm {G\Omega }$. For the lowest ac transimpedance, a bandwidth of $10 \,\mathrm {MHz}$ is achieved. The TIA provides a minimum input-referred current noise density of $1.6\,\mathrm {fA}/\mathrm {\sqrt {Hz}}$. The implemented MEPR has been optimized regarding its high-frequency noise by minimizing its parasitic capacitances. The MEPR shows an inherent shot noise suppression such that its noise stays close to the theoretical thermal noise limit and significantly below the theoretical shot noise limit, even for large dc currents. By using a sub-VSS supply for the MEPR, the asymmetry in its output characteristic is greatly reduced, leading to a linear signal swing of $1.5\,\mathrm {V_{pp}}$ with a THD below $1 \mathrm {\%}$ on a $1.8-\mathrm {V}$ supply. Thanks to this high linearity, large bandwidth, and high dc current dynamic range, the proposed TIA can be used in a wide variety of applications from high-sensitivity, low-bandwidth lock-in detection to transient current sensing with sub-microsecond timing resolutions. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

Injection-locked ring oscillators (ILROs) are widely used for quadrature clock generators (QCG) in multi-lane wireline or optical transceivers because of their low power, low area, and technology scalability. However, locking a four-stage I/Q oscillator with a two-phase injection signal generates imbalances in amplitude and phase, resulting in I/Q phase errors and degraded jitter performance. This paper proposes a modified frequency-domain analysis with amplitude constraint for even-phase ILROs. Combining theoretical derivations with simulation results in 28nm CMOS technology, the behaviors of ring oscillators with partial injection and ILRO-based QCG are discussed and concluded. [ABSTRACT FROM AUTHOR]

This paper presents an advanced offline scheduling scheme to improve the accelerator efficiency, especially for the highly-pruned convolutional neural networks (HP-CNNs). Based on the existing outlier-aware accelerator design, we demonstrate the efficiency drop of HP-CNN processing for the first time, and element-wise channel merging is proposed to make a dense processing sequence even for the highly-pruned model. The dedicated hardware architecture is also presented to process the merged channels with the minimum hardware-level overheads, improving the energy efficiency for handling HP-CNNs by preserving the hardware utilization. We further investigate the optimal size of accumulator and multiplexer, in addition to the number of merged channels, exploiting the attractive energy-performance trade-offs. As a result, unlike the practical HP-CNNs for the on-device solutions, the proposed method enhances the overall efficiency by up to 33% compared to the state-of-the-art schemes. [ABSTRACT FROM AUTHOR]

This paper presents the design and the experimental characterization of a 10 Gb/s electronic driver for silicon Mach-Zehnder modulators (MZMs). This driver is able to operate in harsh environments characterized by radiation levels up to 1 Grad(SiO2) total ionizing dose (TID). To compensate for the detrimental effects that radiation produces on the target 65 nm bulk silicon technology both device- and circuit-level radiation hardened by design (RHBD) techniques are developed and implemented. Extreme TID levels are faced using long-channel transistors with enclosed layout, avoiding the use of p-MOSFETs, and implementing a differential self-biased cascode architecture with common-mode feedback. Band-widening techniques, e.g., inductive peaking, cross-coupled capacitors, and buffer chaining, have been used to improve the driver’s frequency response and reach the targeted data rate. Electrical measurements show 10 Gb/s waveforms with an eye diagram amplitude suitable for MZM driving. Electro-optical measurements performed connecting the electronic driver to a silicon photonic MZM confirm the achievement of a 10 Gb/s system-level operability. The radiation hardness of the driver is verified by exposing the integrated circuit to X-rays. The measurements confirm the ability of the driver to work up to 1 Grad with an eye amplitude reduction of only 10% and a 7% increment in the rise and fall times, validating the effectiveness of the implemented RHBD techniques. [ABSTRACT FROM AUTHOR]

A highly integrated RF power and information receiving system is proposed in this paper. The system consists of an antenna, a rectifier, and an information receiving module. The information receiving module acts as part of the dc load. To realize high integration, a dual-band, dual-circular-polarized shared- aperture antenna is implemented. The antenna consists of a left-circular-polarized element operating at 2.4-GHz band, and a high-gain, right-circular-polarized $2\times 2$ array operating at 5.8-GHz band. The lower-frequency antenna is for communication, while the higher-frequency one is for power transmission. All the elements share the same aperture, and the radiator of lower- frequency antenna acts as the reflector of higher-frequency elements. Accordingly, a class-F rectifier that matches the higher- frequency array is designed and verified, and a system-level demonstration is implemented. Owing to the high isolation on frequency splitting and polarization diversity, the baseband signal can be successfully demodulated under a 30-dB input-power-level difference at two frequency bands. The base-band information can be displayed by an ink screen. The received RF power can be effectively rectified and power the data-processing modules. [ABSTRACT FROM AUTHOR]

Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. Binary Ring-LWE (BRLWE) is a new optimized variant of RLWE, which achieves smaller computational complexity and higher efficient hardware implementations. In this paper, two efficient architectures based on Linear-Feedback Shift Register (LFSR) for the arithmetic used in Inverted Binary Ring-LWE (InvBRLWE)-based encryption scheme are presented, namely the operation of $A\cdot B+C$ over the polynomial ring $\mathbb {Z}_{q}/(x^{n}+1)$. The first architecture optimizes the resource usage for major computation and has a novel input processing setup to speed up the overall processing latency with minimized input loading cycles. The second architecture deploys an innovative serial-in serial-out processing format to reduce the involved area usage further yet maintains a regular input loading time-complexity. Experimental results show that the architectures presented here improve the complexities obtained by competing schemes found in the literature, e.g., involving 71.23% less area-delay product than recent designs. Both architectures are highly efficient in terms of area-time complexities and can be extended for deploying in different lightweight application environments. [ABSTRACT FROM AUTHOR]

Conservative chaotic systems (CCSs) have unique advantages over dissipative chaotic systems (DCSs) in the fields of secure communication and pseudo-random number generators (PRNGs), etc. However, there are relatively fewer reports on CCSs than DCSs. To this end, this paper proposes an effective method for constructing a family of Hamiltonian conservative chaotic systems (HCCSs) by letting any three of the four sub-bodies denoted by 4D generalized Euler equations share a rotation axis. From theoretical analysis to experimental verification, one of the proposed HCCSs is studied thoroughly to demonstrate the effectiveness of this method. The example system has an infinite number of equilibrium points, which belong to either centers or saddles, resulting in hidden chaos. Besides, through the bifurcation diagram, parametric chaotic set, and Lyapunov exponent, richly dynamic behaviors related to parameters are displayed. Moreover, the 3D phase portraits verify that the Hamiltonian energy is conservative. Numerous energy-related coexisting orbits are discovered in this system, such as the coexistence of quasi-periodic orbits, chaotic orbits, and chaotic quasi-periodic orbits. Furthermore, the breadboard-based circuit is implemented to illustrate the HCCS’s physical feasibility. Finally, the PRNG based on the HCCS has excellent randomness in terms of NIST and TESTU01 test results. [ABSTRACT FROM AUTHOR]

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18- $\mu \text{m}$ partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant- $g_{m}$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability $(\sigma /\mu)$ of 1.66 %. Then, two 4T+1R $\mu \text{A}$ -range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09- $\mu \text{A}$ (resp. 0.99- $\mu \text{A}$) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma /\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations. [ABSTRACT FROM AUTHOR]

A novel switching-linear hybrid dynamic regulator architecture with dual-supply low dropout regulators (LDOs) is presented in this paper. This architecture leverages the intrinsic dual supplies to extend the operating range of the LDOs. Furthermore, it increases the thermo-optic tuning efficiency by reducing the LDO dropout voltage through dynamic supply modulation. This architecture is suitable for large-scale thermo-optic tuning in silicon photonics. The efficiency improvement is particularly effective when tracking signals of several adjacent channels are close to each other, e.g., wavelength tuning of a microring array. The principle of this architecture is general and can be implemented using different switching converters and LDOs. A specific design with extensive post-layout simulation results is used to verify the effectiveness of our architecture. Implemented in a 130 nm CMOS process, this design can simultaneously regulate eight output channels with an output swing of 0.8 $\text V_{\text {pp}}$. Its peak efficiency when driving 100 $\Omega $ loads is 92% at 1 V output, and the dynamic efficiency is around 86% when tracking 50 kHz sinusoidal signals. To the best of our knowledge, this is the first time that dynamic supply modulation has been applied to multi-channel thermo-optic tuning of silicon photonic devices. [ABSTRACT FROM AUTHOR]

A phase-locked-based frequency synthesizer – ubiquitously used to generate local oscillation in a communication transceiver – exhibits phase noise and jitter which considerably degrades bit-error rate (BER) and error vector magnitude (EVM) of a digital communication link. This paper presents an analytical study of EVM and BER degradation for a variety of widely used digital modulation schemes. Phase noise and jitter of a generic integer-N phase-locked loop (PLL) as a local oscillator feeding an RF mixer are derived, while accounting for the reference spurs and cyclo-stationarity of the mixer operation as well as the additive noise of the communication link. This jitter model is then utilized to directly study its impact on digital modulation constellations. Specifically, the EVM and BER degradation due to the PLL jitter in communication systems incorporating M-ary phase-shift keying (M-PSK) and ${4^{M}}$ quadrature amplitude modulation (${4^{M}}$ QAM) are analyzed. Comparison between analytical models and system-level simulations verifies an excellent accuracy of these models. [ABSTRACT FROM AUTHOR]

Primary-side regulation (PSR) flyback topology with discontinuous conduction modulation (DCM) mode has been widely used in low-power application due to its high stability, wide input voltage range, low cost, and low standby power. To improve the output power, continuous conduction modulation (CCM) mode is always introduced. However, in CCM mode, conventional PSR voltage-sampling method cannot realize high precision of output voltage or the voltage sampling method requires complex control of high cost. In this paper, a simple digital voltage sampling scheme with two reference voltages outputted from a digital-to-analog converter (DAC) is put forward to trace the “accurate-point” voltage for DCM and CCM modes. In CCM mode, the sampling voltage error of the “knee-point” voltage can be compensated just by inserting DCM switching cycle to obtain the “accurate-point” voltage. Voltage difference between DCM mode and CCM mode will be eliminated, and high precision is easily realized. The proposed method is verified in a 20V, 65W PSR flyback converter. The sampling method only requires a low speed DAC, three comparators and a digital controller. The output voltage precision is within 0.6% with universal input voltage. [ABSTRACT FROM AUTHOR]

The divider is one of the most complex hardware units in Stochastic Computing (SC); even though several new designs have been presented to reduce the computation latency of the conventional divider, all of them still require a considerable number of clock cycles. Moreover, they incur in low performance due to the employed arithmetic computational scheme. In this paper, a Delta Sigma Modulator (DSM) based stochastic divider is proposed. As an entirely digital circuit, the proposed divider offers the best computation latency and accuracy over all existing stochastic dividers found in the technical literature (with a typical reduction between 66.8% and 96.9% in the number of clock cycles and a reduction from $10^{\mathrm {-3.4}}$ to $10^{\mathrm {-3.9}}$ in the average mean square error for a 10-bit resolution). An SC-based Neural Network (NN) is considered as an initial case study to evaluate the advantages of the proposed design in an emerging application; results show that the proposed divider enables an SC-based NN to achieve a higher classification accuracy and hardware efficiency than existing designs. To show the flexibility of the proposed divider design, its application to Sobol-based sequences is also presented; also in this case, its superiority over other designs is confirmed. These features make the proposed design very attractive for hardware-constrained platforms; moreover, such a novel design approach that incorporates ideas from analog/mixed signal circuit design into a digital circuit design, can motivate other researchers to design efficient SC designs using similar schemes. [ABSTRACT FROM AUTHOR]

One key factor affecting the distributed Nash equilibrium (NE) seeking in aggregative games is the unbalanced communication structure for multiple players. Although some results on seeking NE over undirected or weight-balanced graphs were established, how to address the distributed NE seeking problem over general directed communication graphs is still an outstanding challenge. This paper addresses the NE seeking problem for a class of aggregative games with general directed communication graphs. To achieve this objective, two new kinds of distributed discrete-time NE seeking algorithms are developed for aggregative games over fixed digraphs and time-varying digraphs, respectively. In particular, motivated by the heavy-ball method in optimization studies, a momentum term is introduced to the update law of the players’ actions and it is numerically verified that this momentum term accelerates the convergence of the proposed algorithms. For both strongly connected fixed graph and $B$ -strongly connected time-varying graph, it is theoretically proved that the actions of players will converge to the NE of aggregative games for the case of decreasing step-size implemented by the proposed NE seeking algorithms if the cost functions and the aggregation of players satisfy some certain conditions. Finally, the developed NE seeking algorithms are applied to the energy consumption control of plug-in hybrid electric vehicles (PHEVs), which demonstrates the effectiveness of the theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents a primary impulse-radio ultra-wideband (IR-UWB) radar system for real-time short-range localization, e.g., for smart traffic and automotive applications. The radar system consisting of an integrated radar transceiver (TRx) using 45-nm SOI CMOS technology and an FPGA-based signal processing. The efficient transmitter (Tx), which complies with the regulations for both indoor and outdoor applications, modulates and emits a seventh derivative Gaussian pulse. In the receiver (Rx), echo signals will be amplified and sampled in real-time. The echo pulses are recovered by signal processing hardware on the FPGA, which is also used to perform simple classification tasks like user warning. The radar system is compact, portable, and power efficient. The Tx has a high-energy efficiency of $\mathrm {11~ \text {p} \text {J} /pulse}$. The proposed radar system achieves very high signal-to-noise ratio (SNR) and range precision. It has a maximum detection range of $\mathrm {15~m }$ and a range resolution down to $\mathrm {3~ \text {cm}}$. Moreover, a target of interest can be warned with a latency as fast as $\mathrm {16~\mu s }$ by using 1-bit real-time sampling. [ABSTRACT FROM AUTHOR]

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase. [ABSTRACT FROM AUTHOR]

An index of authors and the subjects for the December 2012 issue of "IEEE Transactions on Circuits & Systems. Part I: Regular Papers" is presented.

This paper presents a block-based embedded convolutional neural network (CNN) for gesture classification on field-programmable gate array (FPGA) in real time. Gesture recognition is an important tool to spontaneous interact with human machine interface. Many CNN architectures using RGB images have been proposed for gesture classification. RGB based gesture classification may cause incorrect results under insufficient light or similar gestures. In addition, most of the CNN architectures cannot run in real time on edge devices due to their large number of parameters and DRAM data access. In this paper, a block-based CNN using RGB-D data is proposed for gesture classification. Adding depth images to RGB images boots the classification accuracy. A CNN architecture with block-based feature maps is built for embedded FPGA implementations. The total number of parameters of the proposed RGB-D embedded CNN (eCNN) model is only 0.17M and it achieves 99.96% and 99.88% accuracy with 32-bit floating point and 8-bit fixed point implementation for America Sign Language (ASL) data set. The RTL simulation of the proposed eCNN model has the average inference speed of 0.171 milliseconds at frequency of 250MHz for a single pair RGB-D image. Implemented on a FPGA integrated with Microsoft Kinect v2 achieve an inference time in 19.42 ms which achieves high accuracy and real-time performance. [ABSTRACT FROM AUTHOR]

Passively-integrated memristors are the most prospective candidates for designing high-speed, energy-efficient, and compact neuromorphic circuits. Despite all the promising properties, experimental demonstrations of passive memristive crossbars have been limited to circuits with few thousands of devices until now, which stems from the strict uniformity requirements on the IV characteristics of memristors. This paper expands upon this vital challenge and investigates how uniformity impacts the computing accuracy of analog memristive circuits, focusing on neuromorphic applications. Specifically, the paper explores the tradeoffs between computing accuracy, crossbar size, switching threshold variations, and target precision. All-embracing simulations of matrix multipliers and deep neural networks on CIFAR-10 and ImageNet datasets have been carried out to evaluate the role of uniformity on the accuracy of computing systems. Further, we study three post-fabrication methods that increase the accuracy of nonuniform 0T1R neuromorphic circuits: hardware-aware training, improved tuning algorithm, and switching threshold modification. The application of these techniques allows us to implement advanced deep neural networks with almost no accuracy drop, using current state-of-the-art analog 0T1R technology. [ABSTRACT FROM AUTHOR]

This paper is concerned with the problem of event-triggered optimized control for uncertain nonlinear Itô-type stochastic systems with time-delay and unknown dynamic. By using fuzzy logic systems to approximate two unknown nonlinear functions with the delayed state and current state, respectively. The adaptive identifier is constructed to determine the stochastic system, and the optimized control is designed by using the identifier and adaptive dynamic programming (ADP) of actor-critic architecture. Almost all of the works are concentrated on ADP-based optimal control and it will inevitably cause the complexity of computation and requirements of persistence excitation (PE) assumption. In this paper, the ADP algorithm is obtained based on the negative gradient of a simple positive function (equivalent to the HJB equation), and so the proposed optimal control is simple and can release the PE assumption. Moreover, the event-triggered control approach is proposed to reduce computing burden and communication resources. Furthermore, we prove that the states of system and FLSs parameter errors are semi-globally uniformly ultimately bounded (SGUUB) in mean square via the adaptive identifier and the Lyapunov direct method as well as identifier-actor-critic architecture-based ADP algorithm. Finally, the effectiveness of the proposed method is illustrated through two numerical examples. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on the high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation) without needing a detailed electrical simulation. Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, MDM Laboratory. The parameters extraction procedure is also discussed. The obtained results clearly show that the model proposed in this paper is able to capture the influence of the programming pulse parameters (i.e. pulse duration and height) changes. This is accomplished by the introduction of a parameter, which is related to the specific device technology. [ABSTRACT FROM AUTHOR]

This paper studies the composite refined anti-disturbance control problem of a 2-degree-of-freedom robot arm system modeled by a semi-Markov jump system with multiple disturbances, which includes harmonic disturbances with unknown frequency and amplitude as well as energy bounded disturbances. Firstly, the semi-Markov jump system model is proposed to construct a novel linear model of the 2-degree-of-freedom robot arm subject to two types of disturbances. Next, in order to estimate the uncertain harmonic disturbance, a novel higher order disturbance observer is introduced to convert the uncertain harmonic disturbance into some parameter uncertainty and then estimate the parameter uncertainty. In addition, a corresponding composite anti-disturbance control scheme is formulated to reject and attenuate the above two types of disturbances, respectively. Furthermore, sufficient conditions that can guarantee that the system is stochastically stable are given. Finally, a simulation study of the obtained model is carried out to illustrate the validity of the composite control design method proposed in this paper. [ABSTRACT FROM AUTHOR]

This paper aims to refine and expand the theoretical and application framework of higher-dimensional digital chaotic system (HDDCS). Topological mixing for HDDCS is strictly proved theoretically at first. Topological mixing implies Devaney’s definition of chaos in a compact space, but not vice versa. Therefore, the proof of topological mixing promotes the theoretical research of HDDCS. Then, a general design method for constructing HDDCS via loop-state contraction algorithm is given. The construction of the iterative function uncontrolled by random sequences (hereafter called iterative function) is the starting point of this research. On this basis, this paper put forward a general design method to solve the construction problem of HDDCS, and several examples illustrate the effectiveness and feasibility of this method. The adjacency matrix corresponding to the designed HDDCS is used to construct the chaotic Echo State Network (ESN) for predicting Mackey-Glass time series. Compared with other ESNs, the chaotic ESN has better prediction performance and is able to accurately predict a much longer period of time. [ABSTRACT FROM AUTHOR]

This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental ΔΣ (IΔΣ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and IΔΣ ADCs can both achieve (very) low fixed-pattern noise values. [ABSTRACT FROM AUTHOR]

This paper presents an iterative decimation approach to significantly alleviate the computational burden of centralized controllers applying real-time recursive system identification algorithms in multi-rail power converters. The proposed approach uses an adaptive update rate as opposed to the fixed update rate used in conventional adaptive filters. Also, the step size/forgetting factors vary at different iteration stages. As a result, a reduced computational burden and faster model update can be achieved. Besides, recursive algorithms, such as Recursive Least Square (RLS), Fast Affine Projection (FAP) and Kalman Filter (KF), contain two important updates per iteration cycle; Covariance Matrix Approximation (CMA) update and Gradient Vector (GV) update. Usually, the CMA update requires the greater computational effort than the GV update. Therefore, in circumstances where the sampled data in the regressor does not experience significant fluctuations, re-using the CMA, calculated from the last iteration cycle for the current update can result in computational cost savings for real-time system identification. In this paper, both iteration rate adjustment and CMA re-cycling are combined and applied to simultaneously identify the power converter models in a three-rail power conversion architecture. [ABSTRACT FROM AUTHOR]

A subject and author indexes for the 2010 issue of "IEEE Transactions on Circuits and Systems Part I: Regular Papers" is presented.

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

Using reinforcement learning (RL) algorithm to optimize guidance law can address non-idealities in complex environment. However, the optimization is difficult due to huge state-action space, unstable training, and high requirements on expertise. In this paper, the constrained guidance policy of a neural guidance system is optimized using improved RL algorithm, which is motivated by the idea of traditional model-based guidance method. A novel optimization objective with minimum overload regularization is developed to restrain the guidance policy directly from generating redundant missile maneuver. Moreover, a bi-level curriculum learning is designed to facilitate the policy optimization. Experiment results show that the proposed minimum overload regularization can reduce the vertical overloads of missile significantly, and the bi-level curriculum learning can further accelerate the optimization of guidance policy. [ABSTRACT FROM AUTHOR]

The complexity and size of recent deep neural network (DNN) models have increased significantly in pursuit of high inference accuracy. Chiplet-based accelerator is considered a viable scaling approach to provide substantial computation capability and on-chip memory for efficient process of such DNN models. However, communication using metallic interconnects in prior chiplet-based accelerators poses a major challenge to system performance, energy efficiency, and scalability. Photonic interconnects can adequately support communication across chiplets due to features such as distance-independent latency, high bandwidth density, and high energy efficiency. Furthermore, the salient ease of broadcast property makes photonic interconnects suitable for DNN inference which often incurs prevalent broadcast communication. In this paper, we propose a scalable chiplet-based DNN accelerator with photonic interconnects named ASCEND. ASCEND introduces (1) a novel photonic network that supports seamless intra- and inter- chiplet broadcast communication, and flexible mapping of diverse convolution layers, and (2) a tailored dataflow that exploits the ease of broadcast property and maximizes parallelism by simultaneously processing computations with shared input data. Simulation results using multiple DNN models show that ASCEND achieves 71% and 67% reduction in execution time and energy consumption, respectively, as compared to other state-of-the-art chiplet-based DNN accelerators with metallic or photonic interconnects. [ABSTRACT FROM AUTHOR]

Tree-based machine learning models, like random forests and decision trees, are low-complexity solutions that provide an efficient prediction for a wide range of applications. These models are particularly interesting for energy-constrained platforms since they can be implemented with simple logical operations. Tree-based accelerators are also intrinsically resilient to errors, and this can be leveraged to boost energy efficiency with approximate computing techniques. The key operations in these models are comparisons to constants, making comparators excellent candidates for approximation. This paper presents a technique to approximate comparisons to constants called C2PAx, which is capable of reducing the area and energy of tree-based accelerators. The method consists in finding alternative constants that reduce circuit area while keeping an efficient prediction performance. It is also shown that the selection of the constant parameters directly influences both hardware complexity and model performance, demanding cross-layer optimization. For that, we extend an existing framework that generates VLSI tree-based accelerators, inserting our approximation proposal that allows selecting the constant parameters that maximize energy efficiency at the cost of minor accuracy drops. Simulation results demonstrate that C2PAx outperforms the Don’t Care logic approximation technique when accuracy and energy are jointly considered. C2PAx trades accuracy for significant reductions in the VLSI area, power, delay, and energy consumption compared to precise models. [ABSTRACT FROM AUTHOR]

This paper investigates the fixed-time stabilization problem for a class of nonlinear systems via event-triggered control. The event-triggered mechanism can be applied to the nonlinear system with the coexistence of low-order and high-order nonlinearities. In order to deal with these low-order and high-order terms as well as achieve the objective of fixed-time stabilization, the initial value of the system is divided into two cases, and then the event-triggered controller is designed, respectively. By switching control theory, it is proved that the nonlinear system is globally fixed-time stable under the designed controller and the Zeno behavior can be excluded. Finally, two simulations show that the proposed technology is effective. [ABSTRACT FROM AUTHOR]

Multipliers are essential in implementing nonlinear neuron models, but they take huge implementation costs. Many multiplierless fitting schemes have been proposed to simplify the implementation of nonlinearities in neuron models. To optimize these schemes, this paper presents a nullcline-characteristics- based piecewise linear (NC-PWL) fitting scheme for multiplierless implementations of Hindmarsh-Rose (HR) neuron model. This NC-PWL fitting scheme uses as few line segments as possible to approximate the critical nonlinearity characteristics of the local nullclines. A NC-PWL HR neuron model that reproduces diverse firing patterns of the original one is successfully established. Using off-the-shelf low-cost components, an analog multiplierless circuit is designed for this fitting model and welded on print circuit board (PCB). Meanwhile, by logical shift method, a digital multiplierless circuit with low resource consumption is developed for this fitting model on field-programmable gate array (FPGA) platform. Experimental results of the analog and digital multiplierless hardware implementations verify the numerical simulations and show the simplicity and feasibility of the presented fitting scheme. [ABSTRACT FROM AUTHOR]