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This paper presents a performance analysis of a system for electrochemical impedance spectroscopy (EIS). The system, composed by an analog front-end (AFE) and a custom microcontroller (MCU) board, performs the impulse response (IR) measurement of linear and time-invariant (LTI) systems with pseudo-random excitation signals. As a novelty, a specific AFE for the interfacing of two-terminal resistive and capacitive sensors is covered in detail. The paper proposes, for the first time, a mathematical model to predict the impact of the main noise sources in the measured IR. Thanks to the proposed approach, the AFE and the system’s parameters can be properly designed in order to reduce the error, thus, minimizing the energy-per-error figure of merit (FOM) as well. The AFE is realized as discrete-components circuit and it has been included in a custom MCU-based measurement system as an expansion module. The predicted results from the mathematical model, in terms of noise power, SNR, and measurement error are validated through system-level simulation and experimental measurements. The system performs the IR measurement with 1023 points, showing root-mean-square (RMS) measurement errors of 1% and 1.4% for the tested ADC sampling frequencies of 62.5 kHz and 125 kHz, respectively. These lead to excellent FOM values of 128.9 mJ $\cdot $ %2 and 252.6 mJ $\cdot $ %2 that outstand the state of the art. [ABSTRACT FROM AUTHOR]

This paper proposes a new approach to above- $f_{max}$ power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/ $\sqrt {\text {Hz}}$ is achieved with the proposed receiver. [ABSTRACT FROM AUTHOR]

In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

In this paper, a Takenaka-Malmquist (TM) basis function based equivalent data-model is established by an adaptive rational decomposition for the finite-time interval trajectory tracking control and real-time control of a class of nonlinear systems in the frequency domain. This data model can adaptively learn and match the control process of nonlinear systems. As a result, the proposed trajectory tracking as well as real-time control method can reflect the feature of adaptive learning in order-by-order decomposition, and the feasibility of the proposed method is guaranteed by the convergence of adaptive decomposition by TM basis function under the maximum selection principle (MSP) in Hardy space $H^{2}(\mathbb {D})$. Compared with the traditional model-free control method, this data learning model which matches the control process has obvious advantages in the system model expression and control accuracy. Simulation results at the end of this paper show the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, the distributed optimal containment control problem for multiple nonholonomic mobile robots (NHMRs) differential game is studied via reinforcement learning. An approximation-based optimal control strategy is developed to ensure the optimal performance index and avoid the potential collision among agents. Firstly, the collision avoidance problem considered in this paper is addressed by exploiting a consensus-like interconnection on a directed graph and an error transformation function. Then, on the basis of the optimal backstepping technique, a single critic neural network is adopted to obtain the solution of the coupled Hamilton-Jacobi (HJ) equation, in which an improved learning mechanism is constructed to relax the requirement on initial control conditions. In addition, based on the Lyapunov stability theory, it is proved that all signals in the closed-loop optimal control are uniformly ultimately bounded. Finally, the proposed control protocol is applied to NHMRs system, which verifies that the solution of the coupled HJ equation solves the containment problem of differential game. [ABSTRACT FROM AUTHOR]

In this paper, based on sampled-data control method, we address the stabilization problem for a general class of linear continuous-time fractional systems whose solution contains the Mittag-Leffler function that does not obey the basic exponentiation identity. By considering the infinite memory and hereditary characteristics of fractional-order calculus, we propose a sampled-data controller that guarantees the resulting closed-loop system to be asymptotically stable. Simulation examples are presented to demonstrate the effectiveness of the proposed controller and verify the established results. [ABSTRACT FROM AUTHOR]

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{\mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{\mathbf {e}}$ values. Design theories for obtaining the desired $Q_{\mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure. [ABSTRACT FROM AUTHOR]

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB. [ABSTRACT FROM AUTHOR]

Diffusion-driven instabilities with pattern formation may occur in a network of identical, regularly-spaced, and resistively-coupled cells if and only if the uncoupled cell is poised on a locally-active and stable operating point in the Edge of Chaos domain. This manuscript presents the simplest ever-reported two-cell neural network, combining together only 7 two-terminal components, namely 2 batteries, 3 resistors, and 2 volatile NbOx memristive threshold switches from NaMLab, and subject to diffusion-driven instabilities with the concurrent emergence of Turing patterns. Very remarkably, this is the first time an homogeneous cellular medium, with no other dynamic element than 2 locally-active memristors, hence the attribute all-memristor coined to address it in this paper, is found to support complex phenomena. The destabilization of the homogeneous solution occurs in this second-order two-cell array if and only if the uncoupled cell circuit parameters are chosen from the Edge of Chaos domain. A deep circuit- and system-theoretic investigation, including linearization analysis and phase portrait investigation, provides a comprehensive picture for the local and global dynamics of the bio-inspired network, revealing how a theory-assisted approach may guide circuit design with inherently non-linear memristive devices. [ABSTRACT FROM AUTHOR]

The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22 nm FD-SOI technology running at a clock frequency of 800 MHz. The system achieves a maximum detection throughput of 0.75 Gb/s/mm2 for a $128\times 8$ massive MIMO system. [ABSTRACT FROM AUTHOR]

Eight-switch three-phase post-fault inverter (ESTPI) is widely used as the reconfigured topology of three-phase three-level neutral point clamped DC/AC inverter when open-circuit fault occurs. A key technical challenge for the ESTPI is the post-fault controller design. The existing post-fault control approaches for the ESTPI suffer from the difficulty in trading off the current tracking performance, neutral point voltage (NPV) balancing and common mode voltage (CMV) levels. To solve this problem, this paper proposes an improved predictive current control algorithm. The proposed algorithm contributes to achieve accurate output current tracking while greatly reducing the CMV with a balanced NPV. Simulation and experimental results are presented to validate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

Efficient simulation of switched-mode power conversion circuits is necessary for the analysis and optimization of power electronics. This paper introduces the extended impedance method (EIM) to the simulation and analysis of general switched-mode power converter circuits. By using the EIM method, the conventional impedance concept can be extended to involve more linear time-variant (LTV) and nonlinear devices, such as MOSFET switches and diodes, which are commonly used in switched-mode power conversion circuits. EIM models a circuit network from the component level in the frequency domain, rather than from the system-level constitutive differential equation in the time domain. Compared with the conventional averaging method, EIM can reveal more high-frequency features of a switched-mode converter circuit, in particular, those around the switching instants. A buck converter is taken as a representative example to validate the EIM based analysis. Both the simulation and experimental results prove that EIM provides precise numerical results, which match the real waveform, as the commercial simulators, e.g. PSpice and ADS, do. Moreover, it largely reduces the computational complexity towards more efficient and more flexible steady-state analysis of switched-mode power electronics. [ABSTRACT FROM AUTHOR]

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase. [ABSTRACT FROM AUTHOR]

Multipliers are essential in implementing nonlinear neuron models, but they take huge implementation costs. Many multiplierless fitting schemes have been proposed to simplify the implementation of nonlinearities in neuron models. To optimize these schemes, this paper presents a nullcline-characteristics- based piecewise linear (NC-PWL) fitting scheme for multiplierless implementations of Hindmarsh-Rose (HR) neuron model. This NC-PWL fitting scheme uses as few line segments as possible to approximate the critical nonlinearity characteristics of the local nullclines. A NC-PWL HR neuron model that reproduces diverse firing patterns of the original one is successfully established. Using off-the-shelf low-cost components, an analog multiplierless circuit is designed for this fitting model and welded on print circuit board (PCB). Meanwhile, by logical shift method, a digital multiplierless circuit with low resource consumption is developed for this fitting model on field-programmable gate array (FPGA) platform. Experimental results of the analog and digital multiplierless hardware implementations verify the numerical simulations and show the simplicity and feasibility of the presented fitting scheme. [ABSTRACT FROM AUTHOR]

The analysis of injection-locked clock multipliers (ILCMs) using bang-bang phase detectors (BBPDs) is challenging due to the nonlinear BBPD and the multi-rate injected oscillator. This paper presents an explicit analysis of digital ILCMs using BBPDs and proposed an intuitive approach to optimizing parameters with given noise sources. A time-domain analysis in the single-clock domain is presented to solve the closed-form expression of jitter in the ILCM. The proposed approach exhibits good consistency with simulations, for various design parameters and noise cases. With the predicted input-referred jitter, the equivalent BBPD gain is resolved to derive the frequency-domain noise transfer functions in concise forms. To achieve the desired performance with given specifications, recommended design procedures are summarized based on the proposed analysis and verified by simulations. [ABSTRACT FROM AUTHOR]

This paper focuses on establishing an adaptive boundary observer for fully coupled reaction-diffusions partial differential equations (PDEs) containing unknown parameters. Firstly, the state error system is transformed into an intermediate system by finite dimensional backstepping-like transformation, and then we convert the intermediate system to a target system by infinite dimensional backstepping transformation. Secondly, a least-squares type parameter adaptive law is given. Thirdly, exploiting an ad hoc persistent excitation condition, the exponentially convergent of the observer will be established by applying Lyapunov functional. Finally, we use simulation analysis for Chemical Tubular Reactor model to demonstrate the validity of the results. [ABSTRACT FROM AUTHOR]

In this paper, a class of flexible riser systems modeled by partial differential equations (PDEs) with the backlash is considered. The backlash is formulated as the addition of a linear input and a interference-like term, then an new auxiliary item is introduced to compensate for the impact of this backlash. In addition, the constraint problem for the position and the velocity is also taken into consideration. To solve this constrain problem, the logarithmic barrier Lyapunov function is employed. For the flexible riser system, two kinds of adaptive controllers are proposed under the following two cases. One controller is designed when only the parameter of backlash is unknown. On the basis of this result, the other controller is presented when some system parameters cannot be measured through actual measurement. Then, combing the theory of Lyapunov stability, the two controllers can guarantee the boundedness of all signals in the closed-loop flexible riser system. Further, both the position and the velocity satisfy their corresponding constraint condition. Finally, the simulation example verifies that the proposed control method is effective. [ABSTRACT FROM AUTHOR]

In this paper, a low complexity moving average nested generalized memory polynomial model (MAN-GMP) is proposed for digital predistortion (DPD) of broadband power amplifiers (PAs). As the signal bandwidth increases drastically, the strong nonlinear distortions, especially those induced by the memory effect, are generated from the highly efficient PAs. To compensate for the strong memory effect, a moving average nested envelope memory polynomial (MAN-EMP) model is derived from an accuracy-enhanced GMP model, which offers reduced complexity while suffering from degraded modeling accuracy. The MAN-GMP model is further proposed to improve the modeling accuracy by connecting several memory branches of the MAN-EMP model in parallel. An iterative algorithm is designed to extract the model coefficients efficiently through only one or two iterations. Experimental measurements are carried out on two sub-7 GHz broadband GaN Doherty PAs with up to 200 MHz bandwidth OFDM signals to benchmark the proposed MAN-GMP model against the GMP, the parallel-LUT-MP-EMP (PLUME), the augmented complexity-reduced GMP (ACR-GMP), the generalized twin-nonlinear two-box (GTNTB), and the enhanced Wiener models. The experimental results show that the MAN-GMP model can effectively compensate for the nonlinear distortion of broadband PAs with significant complexity reduction. [ABSTRACT FROM AUTHOR]

This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents an extensive study of linear and logistic regression algorithms implemented with 1T1R memristor crossbars arrays. Using a sophisticated simulation platform that wraps circuit-level simulations of 1T1R crossbars and physics-based models of RRAM (memristors), we elucidate the impact of device variability on algorithm accuracy, convergence rate and precision. Moreover, a smart pulsing strategy is proposed for practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Stochastic multi-variable linear regression shows robustness to memristor variability in terms of prediction accuracy but reveals impact on convergence rate and precision. Similarly, the stochastic logistic regression crossbar implementation reveals immunity to memristor variability as determined by negligible effects on image classification accuracy but indicates an impact on training performance manifested as reduced convergence rate and degraded precision. [ABSTRACT FROM AUTHOR]

Second order memristors are two terminal devices that present a conductance depending on two orders of variables, namely the geometric parameters and the internal temperature. They have shown to be able to mimic some specific features of neuron synapses, specifically Spike-Timing-Dependent-Plasticity (STDP), and consequently to be good candidates for neuromorphic computing. In particular, memristor crossbar structures appear to be suitable for implementing locally competitive algorithms and for tackling classification problems by exploiting temporal learning techniques. On the other hand, neuromorphic studies and experiments have revealed the existence of different kinds of plasticity and have shown the effect of calcium concentration on synaptic changes. Computational studies have investigated the behavior of spiking networks in the context of supervised, unsupervised, and reinforcement learning. In this paper, we first derive a simplified, almost analytical, model of a second-order memristor, only involving two variables, the mem-conductance, and the temperature, directly attributable to the synaptic efficacy and to the calcium concentration. Then we study in detail the response of a single memristive synapse to the most relevant plasticity models, including cycles of spike pairs, triplets, and quadruplets at different frequencies. Finally, we accurately characterize memristor spiking networks as discrete nonlinear dynamic systems, with mem-conductances as state variables and pre and postsynaptic spikes as inputs and outputs, respectively. The result shows that the model developed in this manuscript can explain and accurately reproduce a significant portion of observed synaptic behaviors, including those not captured by classical spike pair-based STDP models. Furthermore, under such an approach, the global dynamic behavior of memristor networks and the related learning mechanisms can be deeply analyzed by employing advanced nonlinear dynamic techniques. [ABSTRACT FROM AUTHOR]

The dynamics of modern hybrid power systems are characterized by behaviors at different timescales, typically separated by several orders of magnitude. In this paper we apply the envelope-following method to hybrid power systems simulations, in which single-phase and three-phase representations of a power system co-occur. This simulation method is well suited for handling coexisting behaviors occurring at different timescales. Compared to the simulation approaches present in the literature, the envelope-following method does not need to continuously switch between two separate simulation engines, but rather automatically handles instantaneous variations in the dynamics of the system, such as faults or topology changes. Additionally, given the vast penetration of power electronic components in modern electricity networks, employing the envelope-following method allows using a vast array of numerical algorithms that have been developed over the years to simulate electrical and electronic circuits. The proposed approach is validated by means of power systems case studies of increasing complexity. [ABSTRACT FROM AUTHOR]

A random sampling-and-averaging (RSA) technique based on stochastic Monte Carlo methods is described in this paper for enhancing the accuracy of single-photon arrival-time measurements down to sub-picosecond ranges in emerging quantum applications. The theoretical variances of both synchronous and asynchronous RSA techniques are presented in the mathematical formats and experimentally verified by the Monte Carlo simulations. Meanwhile, the methodology of converting the mathematical models into an almost all-digital low-power integrated-circuit is elaborated by a circuit-level example with the instruction of setting circuit parameters. Along with the superior measurement resolution, scalable dynamic ranges, high linearity, high noise immunity, and low power/area consumption, the primary limitation of the RSA techniques has also been addressed for the forthcoming conversion-rate enhancement techniques. [ABSTRACT FROM AUTHOR]

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 $\text{G}\Omega $ and 700 $\text{G}\Omega $ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-theoretic analysis of a NbO2-Mott memristor fabricated at Hewlett-Packard Labs. It investigates mechanisms behind the origin of complexity based on local activity, which characterizes the behavior of this outstanding nanodevice. We propose an accurate, particularly simplified version of a recently introduced physical model suitable for large-scale circuit simulations. Following the concept of local activity, we then conduct a small-signal circuit-theoretic derivation of the impedance and associated small-signal equivalent circuit elements to analyze device stability and frequency response. Finally, our analysis reveals locally active operating regions, as well as regions where the device dynamics are positioned on the edge of chaos. The latter regions are crucial for designing bio-inspired computing systems. [ABSTRACT FROM AUTHOR]

Memristors are widely used to construct multi-scroll/wing chaotic systems with complex dynamics. However, the generation of a multi-scroll/wing attractor is typically not induced by the memristor but depends on other nonlinear functions in the system, which does not take advantage of the unique features of the memristor for chaos-based applications. To address this issue, the present paper introduces a memristor coupling (MC) method to construct a novel memristive Sprott A system (MSAS) through coupling a flux-controlled memristor with multi-piecewise linear memductance into the chaotic Sprott A system. From theoretical analysis and numerical simulations, the MSAS is shown to be able to generate any number of multi-type hidden attractors, including multi-one-scroll, multi-double-scroll and multi-double-wing hidden attractors. In addition, it has two kinds of multistabilities, that is, heterogeneous multistability and homogeneous multistability. Based on these unique properties, different numbers of coexisting heterogeneous hidden attractors and coexisting homogeneous hidden attractors are derived respectively by switching the memristor initial states. These interesting dynamical properties are comprehensively investigated using nonlinear analysis tools. Furthermore, hardware experiments are implemented to demonstrate the feasibility of the MSAS and the effectiveness of the MC method. Finally, a new pseudo-random number generator (PRNG) is proposed to explore the practical applications of the MSAS. Performance evaluation results verify the high-quality randomness of the designed PRNG. [ABSTRACT FROM AUTHOR]

Recently, integrating ferroelectric materials with nanotransistors such as carbon nanotube field-effect transistors (CNTFETs) has opened new doors for demonstrating a new generation of ultra-miniature circuits and systems. Utilizing the negative differential resistance effect in negative capacitance CNTFETs (NC-CNTFETs) has spurred the efforts for designing ultra-compact ternary circuits and systems similar to their binary structures. This paper presents an ultra-efficient ternary image edge detection hardware using NC-CNTFET technology. The proposed hardware is endowed with a noise reduction circuitry to mitigate the noise effects. Using four $1\times 3$ kernels and concatenating the image pixels, the proposed ternary hardware has been designed using only 50 transistors. The proposed ternary hardware at the circuit level shows, on average, 74% improvements regarding power delay-product (PDP) compared to the CNTFET-based counterparts. Our comprehensive simulations indicate that the proposed NC-CNTFET-based hardware shows a 40% improvement in data loss, 2.2 times improvement in performance ratio, and 1.14 times improvement in Pratt’s figure-of-merit, respectively, compared to the related designs. Our results accentuate that the proposed NC-CNTFET-based ternary hardware is a breakthrough achievement in demonstrating ultra-efficient and noise-immune ternary image processing circuits beyond the conventional binary counterparts. [ABSTRACT FROM AUTHOR]

S-type locally-active memristor (LAM) has a great potential for brain- inspired neuromorphic computing, where the S-type LAM-based oscillator is a fundamental building block. Concerning the S-type LAM, this paper constructs a material-independent model in simple mathematical expression, which can be relatively easily analyzed. By biasing the memristor into the locally- active region, and connecting it with a capacitor, a second-order oscillator can be built. The small-signal equivalent circuit of the memristor and its frequency response are applied to determine the period oscillation frequency range and compensation capacitance. Hopf bifurcation theory is used to analyze oscillation mechanism of the second-order circuit and appropriate capacitance. By adding an extra inductor into the second-order oscillator, a novel third-order chaotic circuit is developed, where a saddle-focus is derived to create chaos. Its dynamic characteristics are investigated via Lyapunov exponents, bifurcation diagrams, dynamic route map, and so on. The local activities of the single memristor, second-order oscillator, and third-order chaotic circuit are verified through the mathematical analysis. Finally, physical circuit realizations of the S- type LAM-based oscillators, including the memristor emulator, are presented. Both simulation and experimental results demonstrate the practicability of the proposed mathematical model and the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

Conventional design and optimization of passive compensation network (PCN) for inductive power transfer (IPT) system are based on specific topologies. The demerits of this design method are: i) The topology is mostly chosen by experience; ii) The design parameters are not multi-objective optimal. Aiming at these issues, this paper proposes an optimal PCN design scheme based on evolutionary algorithm (EA) to synchronously optimize the topology and parameters of PCN for IPT system. Firstly, a unified mathematical model of the PCN is presented and derived by transmission matrix. Then, according to the mathematical model, the multi-objective functions (such as output fluctuation and efficiency) as well as the constraints (such as load and coupling coefficient) for the optimal PCN design are established. The EA based multi-objective optimal PCN design algorithm is further constructed. Six optimal results are obtained using the algorithm, and one optimized PCN having minimum output current fluctuation and high-efficiency is chosen to validate the effectiveness of the proposed design scheme in experiment. For the given IPT system with the optimized PCN, the maximum fluctuation of output current is no more than 11%, within 200% of load variation and about 77% of coupling variation. [ABSTRACT FROM AUTHOR]

The approximate (multiplier-less) two-dimensional discrete cosine transform (DCT) is a widely adopted technique for image/video compression. This paper proposes a deterministic low-complexity approximate DCT technique that accurately configures the size of the transform matrix (${T}$) according to the number of retained coefficients in the zigzag scanning process. This is achieved by establishing the relationship between the number of retained coefficients and the number of rows of the ${T}$ matrix. The proposed technique referred to as the zigzag low-complexity approximate DCT (ZLCADCT), when compared with approximate DCT (ADCT), decreases the number of addition operations and the energy consumption while retaining the PSNR of the compressed image. In addition, the ZLCADCT eliminates the zigzag scanning process used in the ADCT. Moreover, to characterize the deterministic operation of the ZLCADCT, a detailed mathematical model is provided. A hardware platform based on FPGAs is then utilized to experimentally assess and compare the proposed technique; as modular, deterministic, low latency, and scalable, the proposed techniques can be implemented upon any change in the number of retaining coefficients by realizing only a partial reconfiguration of the FPGA resources for the additional required hardware. The extensive simulation and experimental results show the superior performance compared to previous ADCT techniques under different metrics. [ABSTRACT FROM AUTHOR]

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior. [ABSTRACT FROM PUBLISHER]

This paper studies an $H_{\infty }$ model reduction problem for interval frequency negative imaginary (IFNI) systems. For a given IFNI system, our goal is to find a reduced-order IFNI system satisfying a pre-specified $H_{\infty }$ approximation error bound over the finite-frequency interval. Necessary and sufficient conditions in terms of matrix inequalities are derived for the existence and construction of an $H_{\infty }$ reduced-order IFNI system. An improved iterative algorithm is provided to solve the matrix inequalities and to minimize the $H_{\infty }$ approximation error. The proposed method is further clarified via the application to the electrical circuits, such as high-order Sallen–Key low-pass filter, piezoelectric tube scanner, and RLC circuit. The simulation results on these electrical circuits are compared with the finite-frequency interval Gramians-based model reduction method both in the frequency domain and time domain. [ABSTRACT FROM AUTHOR]

This paper deals with modeling and simulation of a new family of two-terminal devices fabricated with vanadium dioxide material. Such devices allow realization of very compact relaxation nano-oscillators that can be connected electronically to form arrays of coupled oscillators. Challenging applications of oscillator arrays include the realization of multiphase signal generators and massively parallel brain-inspired neurocomputing. In the paper, a circuit-level model of the vanadium dioxide device is provided which enables extensive electrical simulations of oscillator systems built on the device. The proposed model is exploited to explain the dynamics of vanadium dioxide relaxation oscillators as well as to accomplish a robust parameter design. Applications to the realization of voltage-controlled oscillators and of multiphase oscillator arrays are illustrated. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

This paper presents a compact model for threshold self-compensated rectifiers that can be used to optimize circuit parameters early in the design phase instead of time-consuming transient simulations. A design procedure is presented for finding the optimum aspect ratio of transistors used in the converter and number of rectifying stages to achieve the maximum power conversion efficiency. In the presented analysis, the relation between the power conversion efficiency and the load current over the variation of the output dc voltage is used to find the optimum design parameters. Accurate approximation of the charge entering to and exiting from the rectifier during the steady state helps to get good agreement between the predicted output dc voltage and simulation results under different load current values. Using the Enz-Krummenacher-Vittoz model for the MOS transistor, an accurate formula is derived for optimization. The ability of the model in weak, moderate, and strong inversion region aids to find the optimum design parameters for broad range of RF voltage variation. The presented formula for estimating the optimum size and number of stages shows good agreement with simulations. Further validation is provided by comparing model predictions with measurement results of a four-stage self-compensated rectifier operating at 900 MHz, which is implemented in a commercial 0.18- \mu \textm partially-depleted silicon-on-insulator process. [ABSTRACT FROM PUBLISHER]

With the Internet of Things (IoT) paradigm promising to deploy trillions of sensors, the search is on for effective means to efficiently derive useful information from the flood of sensor data through efficient hardware preprocessing. Of particular interest are computational paradigms that get their inspiration from biological sensory systems that seamlessly extract relevant information through highly efficient analog signal processing. Functions, such as feature extraction, learning, or recognition, could especially benefit from bio-inspired architectures. As an example in the case, this paper presents a bio-inspired analog gas sensing frontend for an artificial olfactory system. The analog front end implements a novel trainable feature extraction algorithm for metal-oxide gas sensor arrays. The algorithm extracts one composite feature of all analytes by performing the gradient decent algorithm during training and transforms the sensor responses into concentration-invariant spike patterns. An integrated circuit realization of the algorithm, implemented in a 65-nm CMOS technology, supports six-input channels, uses subthreshold analog circuits, and consumes 519-nW/channel in the training mode, and 463-nW/channel in the recognition mode. [ABSTRACT FROM PUBLISHER]

Energy efficiency is highly desirable for sensing systems in the Internet of Things. A common approach to achieve low-power systems is duty cycling, where components in a system are turned OFF periodically to meet an energy budget. However, this paper shows that such an approach is not necessarily optimal in energy efficiency, and proposes guided processing as a fundamentally better alternative. The proposed approach offers: 1) explicit modeling of performance uncertainties in system internals; 2) a realistic resource consumption model; and 3) a key insight into the superiority of guided processing over duty cycling. Generalization from the cascade structure to the more general graph-based one is also presented. Once applied to optimize a large-scale audio sensing system with a practical detection application, empirical results show that the proposed approach significantly improves the detection performance (up to 1.7 times and 4 times reduction in false alarm and miss rate, respectively) for the same energy consumption, when compared with the duty-cycling approach. [ABSTRACT FROM PUBLISHER]

Analog matrix computing (AMC) with resistive memory implies naturally massive parallelism and in-memory processing, thus representing a promising solution for accelerating data-intensive workloads in many applications. In AMC circuits, the interconnect resistances residing in the crosspoint resistive arrays arise as a main non-ideal factor degrading the computing accuracy. Simulating and optimizing the circuits are of fundamental importance for large system integration. In this work, we develop a physics-based iterative algorithm to quickly model the matrix-vector multiplication (MVM) operation of crosspoint resistive array with interconnect resistances, thus quadratically reducing the time complexity of circuit simulation. In addition, we propose a new MVM circuit for matrix with negative values, in parallel with the conventional column-wise splitting (CS) and row-wise splitting (RS) circuits. The circuit is based on the conductance compensation (CC) strategy to realize a simplified RS scheme. The discrete Fourier transform (DFT) is implemented using this circuit as a case study. Simulation results reveal that the computing error caused by interconnect resistances is remarkably reduced in the CC-RS circuit. Also, the CC-RS scheme is demonstrated to be more immune to device variations and source/sink resistances. Our results provide an efficient modeling method together with an optimized approach for AMC circuits with non-idealities. [ABSTRACT FROM AUTHOR]

This article proposes a broadband high-efficiency parallel-circuit (PC) class-EF power amplifier (PA) along with a quarter-wavelength stub for the first time. By adding a reactive element ${X}$ , the design space is expanded so that the impedance terminations of the fundamental and harmonics are no longer fixed points. Based on the broadband capability of the proposed structure, using a GaN HEMT transistor, a proof-of-concept circuit implemented with the Chebyshev impedance transformation network is designed and fabricated. Experimental results demonstrate a high-efficiency broadband PA operating from 2.6-3.9 GHz, with the average efficiency of 71.5%, the measured output power (${P}_{\textit {out}}$) of 38.8-40.9 dBm and the power gain of 8.5-10.6 dB. [ABSTRACT FROM AUTHOR]

The article provides an optimal synthesis of nonuniform transmission line structural elements, where resonant frequencies have a special placement. It is possible to improve the functionality of dual-mode resonators, which use these transmission segments. The optimal synthesis means that we obtain the special ratio between resonance frequencies of structural elements and have the minimum of parameter ${m}={Z}_{\text {0max}}/{Z}_{\text {0min}}$. We used the parametric synthesis for optimize proposed structure. It leads to stepped-impedance transmission line segments (SILS) which have the resonant frequencies with required placement and ${m}= {m}_{\text {min}}$. Two SILS pairs are synthesized. Two ends of one pair are open-circuited and the other pair is short-circuited. We added different stubs to the middle of proposed SILS. As result, four new dual-mode resonators with enhanced functions are designed. All dual-mode resonators have an extended stopband. The dual-mode resonators have reduced length relative to a half-wave resonator. The resonators allow increasing their operating frequencies. These resonators are very promising for use in dual-band BPF, so we can change the placement of one passband to another in the range $1.46 \le {f}_{2}/{f}_{1} \le 6.47$. The measured and simulated results of two microstrip filters with new structural elements are offered. [ABSTRACT FROM AUTHOR]

The influence of coupling of oscillators in phase-locked loops (PLLs) was studied here. Particularly, numerical analyses based on nonlinear differential equations of the self- and mutual coupling systems were performed and compared with the results of the linear approximation model under synchronous conditions. The analysis revealed that coupling using the reference clock caused greater PLL instability than that caused by self-coupling for a given coupling strength. This shows that the phase error of mutual coupling exhibits the same behavior as that of reference-clock coupling in the single PLL under synchronous conditions, and the noise sensitivity of mutual coupling is twice that of the reference-clock coupling. In addition, the phase error of mutual coupling in the quasi-synchronous condition strongly depends on the relationship between the frequency difference of the two PLLs and the PLL bandwidth. We designed and fabricated the test circuits for theoretical verification using the 0.18- $\mu \text{m}$ standard CMOS process. From the measurements, adjustment of the timing difference between the two PLLs is effective in mitigating mutual coupling under synchronous conditions. Moreover, we implemented mutual injections between two oscillators in the test circuit and confirmed their effectiveness. The proposed methods will be useful for achieving the compact and effective cancellation of the mutual coupling between PLLs. [ABSTRACT FROM AUTHOR]

In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT. [ABSTRACT FROM PUBLISHER]

This paper is concerned with the problem of distributed federated Kalman filter fusion (DFKFF) for a class of multi- sensor unreliable networked systems (MUNSs) with uncorrelated noises. An optimal DFKFF algorithm of MUNSs without buffer is presented, and rigorously proved to be equivalent to centralized optimal Kalman filter fusion (COKFF) algorithm of MUNSs without buffer. Finite length buffers deal with measurement delay or loss, and a suboptimal DFKFF algorithm of MUNSs with finite length buffers is proposed based on the optimal local Kalman filter with a buffer of finite length for each subsystem. Compared with COKFF algorithm of MUNSs with buffers, the proposed DFKFF algorithm of MUNSs with buffers has stronger fault-tolerance ability. Two simulation examples are given to illustrate the effectiveness of the proposed approaches. [ABSTRACT FROM PUBLISHER]

This paper presents a systematic approach for the statistical simulation of nonlinear networks with uncertain circuit elements. The proposed technique is based on spectral expansions of the elements' constitutive equations (I-V characteristics) into polynomial chaos series and applies to arbitrary circuit components, both linear and nonlinear. By application of a stochastic Galerkin method, the stochastic problem is cast in terms of an augmented set of deterministic constitutive equations relating the voltage and current spectral coefficients. These new equations are given a circuit interpretation in terms of equivalent models that can be readily implemented in SPICE-type simulators, as such allowing to take full advantage of existing algorithms and available built-in models for complex devices, like diodes and MOSFETs. The pertinent statistical information of the entire nonlinear network is retrieved via a single simulation. This approach is both accurate and efficient with respect to traditional techniques, such as Monte Carlo sampling. Application examples, including the analysis of a diode rectifier, a CMOS logic gate and a low-noise amplifier, validate the methodology and conclude the paper. [ABSTRACT FROM AUTHOR]

This paper proposes a theory of harmonic filters and their mathematical models, applicable to periodically time varying (PTV) systems perturbed by a large periodic signal. The harmonic filters are based on a series of finite time delay and weighted sum operations, which allow selection or rejection of an input fundamental tone and/or its harmonics in a periodic manner. The harmonic filters are essentially array processors and can be analogous to digital FIR filters. The paper discusses optimum ways of choosing filter coefficients, time delays, and weights for the harmonic rejections and selections, equivalent to lowpass filters and highpass filters, respectively. Mathematical models for effects of hardware mismatches, weight and delay mismatches, on the filtering performance are provided and verified through ADS behavioral statistical simulations. The theory can be applicable to design quasi-sinusoidal mixers for a quality spectral purity, or harmonic carrier modulators and demodulators for high frequency applications . [ABSTRACT FROM AUTHOR]

The failure probabilities of industrial SRAM cells fall below the ppm (10−6) range, disqualifying the computational-intensive Monte-Carlo simulations for efficient robustness assessment. Starting from a novel two-dimensional threshold voltage imbalance representation, we propose a new methodology for fast and accurate prediction of the subthreshold SRAM hold stability failure rate. The probability is derived in a closed form which involves the transistor threshold-voltage standard deviations and only requires the two quick DC extractions of the worst- and best-case static noise margins. We validate our approach on a Six-Transistor (6T) bitcell in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology. Our method turns out to be especially insightful for comparative and sensitivity analyses, for instance to study the effect of supply voltage downscaling or temperature variations. Finally, we show that the achieved accuracy and the capability of estimating extremely low failure probabilities (down to 10−9), combined with the important gain in simulation and post-processing cost, makes our methodology attractive compared to other recent modelling works. [ABSTRACT FROM AUTHOR]

This article revisits the concept of “noise measure” and its importance in designing high-frequency low-noise amplifiers. A new derivation is offered which is simpler than the original derivation of Haus and Adler. Several examples are used to calculate the minimum noise measure of a CMOS amplifier. It is also shown that “noise cancellation” techniques cannot improve the minimum noise measure. [ABSTRACT FROM AUTHOR]

Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discussed in this paper. Digital applications such as memory and logic require a model that is highly nonlinear, simple for calculations, and sufficiently accurate. In this paper, a new memristive device model is presented—TEAM, ThrEshold Adaptive Memristor model. This model is flexible and can be fit to any practical memristive device. Previously published models are compared in this paper to the proposed TEAM model. It is shown that the proposed model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models. [ABSTRACT FROM PUBLISHER]